Power consumption measurement and temperature recording during granulation

Graphene is assumed that it can be used in analog electronics because of its extraordinary electronic features. But nowadays it is investigated in digital logic gates due to the tunability of Fermi energy level. For making a promising logic gate, graphene is now exercised in correlation with the using of optics law. Transport properties in a doped graphene are extensively determined by measurement of incident angle. From which an important property of a device like “resistance of interface” can be extracted. Moreover, width of the graphene is one of the issues to be thought. By minimizing resistance of interface and maximizing the width of graphene, considerable power consumption can also be determined. In this paper, we will observe the electron transmission probability depending on the variation of incident angle of light of an interface. Then, we will calculate the resistance of interface. We will investigate the ambipolar characteristics by observing dc conductivity of graphene. At last, we will measure the power consumption of the device by tradeoff between the resistance and width of graphene.

Power consumption analysis of constant bit rate video transmission over 3G networks

MuMMI (Multiple Metrics Modeling Infrastructure) environment is an infrastructure that facilitates systematic measurement, modeling, and prediction of performance, power consumption and performance-power tradeoffs for parallel systems. MuMMI builds upon three existing frameworks: Prophesy for performance modeling and prediction of parallel applications, PAPI for hardware performance counter monitoring, and PowerPack for power measurement and profiling. In this paper, we present the MuMMI framework, which consists of an Instrumentor, Databases and Analyzer. The MuMMI Instrumentor provides automatic performance and power data collection and storage with low overhead. The MuMMI Databases extend the databases of Prophesy to store power and energy consumption and hardware performance counters' data with different CPU frequency settings. The MuMMI Analyzer extends the data analysis component of Prophesy to support power consumption and hardware performance counters, and it entails performance and power modeling, performance-power tradeoff and optimizations, and web-based automated modeling system. Currently, our MuMMI online automated performance and power modeling system uses four modeling techniques: curve fitting, parameterization, kernel coupling and performance-counters-based, we discuss the effort to automate the process of developing performance and power models for scientific applications online, and focus on exploring performance-counters-based performance and power modeling. The MuMMI environment is able to aid in performance and power data measurement, storage, modeling and prediction of scientific applications on XSEDE resources in XSEDE community.

Effect of the type and number of high-speed impellers installed on a common shaft on the power characteristics was investigated in water and glucose solutions of different concentration. Different configurations of the Rushton or Smith turbines, pitched blade turbines, propeller, and A 315 impeller were tested. Measurements of power consumption were carried out within the transitional and turbulent regime of the fluid flow using the strain gauge method. Baffled agitated vessels with inner diameter of 0.288 m and 0.634 m were used for the experiments. Liquid height in the vessels was equal to the vessel diameter or it was twice higher. The relative power consumption was compared for different configurations of the impellers.

Characterizing, Modeling, and Accurately Simulating Power and Energy Consumption of I/O-intensive Scientific Workflows

Method of the battery-operated electronic devices power consumption measurement has been developed. Proposed method allows to estimate the device operating time from one set of batteries. The method is based on the analysis of the large capacitor discharge by the electronic device powered from it. Simple measuring setup for measurement is used. Setup consists of a constant current source, a large capacitor composed of several parallel electrolytic capacitors and a digital oscilloscope. Results of the power consumption measurements and average current consumption measurement accuracy estimation is presented.

Power analysis is an important and efficient mean for side channel attacks on security applications. By monitoring devices' power consumption during various operations it is possible to collect security information (e.g. the encryption key). These power drop-offs counter effects could be reduced or even eliminated, if accurate power estimations could be achieved on the early design cycles. It is crucial for the designers, to be able to evaluate accurately the power consumption during the development process, especially for the widely used, power consuming, security algorithms. This paper presents and compares the estimated and measured power consumption of security algorithms on both Xilinx and Altera FPGAs. The estimation numbers are produced using each vendor's commercial power estimation tool.The differences between measured and estimated power consumption, varied from 15.52% to 208% for the Xilinx devices and from 5.64% to 32.15% for the Altera device.As a result, although Altera's PowerPlay power estimation tool gene/rated more accurate results than Xilinx's Xpower tool, none of them seems to be yet mature enough for the very demanding security era.

Usability is key to achieve quality in software products. The client applications with a high score in usability might impact on the power consumption when they are run in a PC. For this reason, energy savings turn to be critical in green software systems. In this paper the relationship between the usability evaluations of the GUIs and the power consumption measurements of the main components of a PC were analysed. A set of 5 web-based personal health records (PHRs) were selected as a case study. The usability assessment was performed by an expert, employing the 14 principles of design by Alan Dix as heuristics. They were scored on a Likert scale after performing a collection of common tasks in the PHRs. At the same time, an equipment to measure the energy consumption of hard disk drive, graphics card, processor, monitor and power supply was used. Spearman’s index was studied for the correlations between the usability assessments and the power consumption measurements. As a results, some weak relationships were found. A total of 5 usability heuristics were observed to may influence energy consumption when they were considered in the implementation of the PHRs. These heuristics were the following ones: consistency, task migratability, observability, recoverability and responsiveness. Based on the results, the usability principles of design cannot always be related to lower energy consumption. Future research should focus on the tradeoffs between usability and power consumption of client applications when they are used in a computer.

In this paper, an extensive review of the available publications about comparing estimations versus measurements of power consumption in FPGA technology is carried out. This study reveals that the variety of experimental setups makes it difficult to elaborate solid studies departing from the results of different researchers using meta-analysis techniques. To mitigate this problem, we propose a procedure to standardize the setup of FPGA power estimation experiments. The goal is to make as close as possible power estimations and their corresponding actual on-chip measurements. The main idea is to use a fixed arrangement composed by a parameterized pattern generator block at the input, together with a set of interchangeable IP cores utilized as reference circuits. All the blocks are mapped together inside the FPGA sample, being the clock and reset lines the sole input signals. Thus, both power estimation and actual measurements are performed to the whole system in identical conditions. In order to illustrate the method, the paper includes some examples of the proposed methodology for different cores. A set of 25 circuits have been tested in two FPGA families, obtaining relative errors in power estimation between –61.5% and 9.2%.

While distributed computing infrastructures can provide infrastructure-level techniques for managing energy consumption, application-level energy consumption models have also been developed to support energy-efficient scheduling and resource provisioning algorithms. In this work, we analyze the accuracy of a widely-used application-level model that have been developed and used in the context of scientific workflow executions. To this end, we profile two production scientific workflows on a distributed platform instrumented with power meters. We then conduct an analysis of power and energy consumption measurements. This analysis shows that power consumption is not linearly related to CPU utilization and that I/O operations significantly impact power, and thus energy, consumption. We then propose a power consumption model that accounts for I/O operations, including the impact of waiting for these operations to complete, and for concurrent task executions on multi-socket, multi-core compute nodes. We implement our proposed model as part of a simulator that allows us to draw direct comparisons between real-world and modeled power and energy consumption. We find that our model has high accuracy when compared to real-world executions. Furthermore, our model improves accuracy by about two orders of magnitude when compared to the traditional models used in the energy-efficient workflow scheduling literature.

The subsystem in a smartphone means its hardware components, such as the CPU, GPU, and screen. Accurately estimating subsystem power consumption of commercial smartphones is necessary for applicable to wide research areas. Current subsystem power estimation techniques are mostly based on power models, resulting in considerable errors for various types of power consumption behaviors. These include (1) asynchrony between the measured power consumption and the corresponding workload statistics, and (2) nonlinearity concerning CPU idle states, pixels colors of AMOLED screen, and GPU workload statistics. In this study, we propose a novel utilization-based, subsystem power estimation method for a smartphone, namely Clustering and Symbolic Regression (CSR) that takes these power consumption behaviors into account so as to increase power estimation accuracy. To address asynchrony, we cluster the subsystem workload statistics into synchronous and asynchronous groups by employing affinity propagation clustering. To address nonlinearity, we employ symbolic regression for fitting measured power consumptions with respect to subsystem workload statistics. We compare our approach with various power estimation methods, Linear Regression Model (LM), Genetic Programming (GP), and Support Vector Regression (SVR). The results show Mean Absolute Percentage Error (MAPE) reduction between 23.61 and 42.55 percent on the estimated power consumption of a simple (Nexus S) and complex (Galaxy S4) smartphone subsystems.

The accurate measurement of a server's power consumption when running realistic workloads enables characterization of its energy efficiency and helps to make better provisioning and workload placement decisions. Information on the energy efficiency of a server for a given target workload can greatly influence such decisions and thus the final energy efficiency of a cluster or data center. However, measuring energy efficiency and power consumption of server applications has become challenging as applications are often distributed or require work intensive configuration, setup, and specialized load drivers for reproducible testing. As a result, it may be not feasible to perform tests using the actual workload that is to be deployed. We introduce an approach to create small-scale workloads that emulate the power consumption-relevant behavior of an application by deliberately triggering specific power relevant performance counter events. These workloads can then be easily deployed on a target server for fast and efficient power characterization. We validate the proposed approach by approximating the power consumption behavior of different workloads at multiple load levels. We show that our approach is capable of producing small-scale workloads that reflect the power consumption behavior of their reference applications over multiple load levels with a minimum error of less than 1%.

Street Lighting Lamp (SLL) is the city or regency government public service for security and regularity of the street area environment.As the number of SLLs increased there are illegal installation of SLL making the unpredictable billing for the government and increasing the budget. To solve the problem, the power consumption measurement must be implemented to get the efficient billing. There are such devices can be used as measurement or meterization like KWH-meter or MeasurementLimiter Device. Keywords: Street Lighting Lamp (SLL), power consumption, KWH-meter, MeasurementLimiter Device

The collection of Floating Car Data (FCD) is very important for dynamic traffic forecasts. For this purpose, sensor notes in cars are supposed to transmit traffic information via Long Term Evolution (LTE). In this paper, we evaluate this data transmission with regard to several Key Performance Indicators (KPIs) for a channel aware transmission. These indicators are the negative impact on human communication, the power consumption of the mobile devices and the local distribution of cars sending FCD in the scenario. As methodology for performance evaluation a close-to-reality parameterized Markovian model, laboratory data rate as well as power consumption measurements and ray tracing simulations are used. By applying channel aware transmission the Quality of Service (QoS) level of human communication can be obtained and simultaneously the power consumption is significantly reduced. In addition, the fraction of active FCD devices on the highway can be increased.

Low-power circuit designs are required for battery-operated devices. A transistor needs to be small enough to be integrated onto a single chip. Therefore, CNTFET technology has been widely used to design nanoscale circuits for energy-efficient integration. Multiple-valued logic is utilised to reduce the circuit complexity by minimizing the interconnections. Compared to binary circuits, MVL circuits are more noise sensitive. As a result, it’s essential to consider noise margin into account when designing sustainable and reliable ternary circuits. The paper proposes a standard ternary inverter and compares noise margin, power consumption, delay, and PDP measurements with existing standard ternary inverters. The proposed STI has a 68.6% higher noise margin than the existing designs and 82%, 80%, and 91% improvements in power consumption, PDP, and delay, respectively, over existing circuits.