Power Electronic Devices and Systems Based on Bulk GaN Substrates

This study analyzes the changes in the density of interface traps (DIT) for various atomic layer deposition (ALD) gate dielectric films on gallium nitride (GaN) devices fabricated on bulk GaN substrates. Each film type has been chosen with an optimized insulator/semiconductor interface obtained through chemical cleans or post deposition annealing (PDA). Reduction in dielectric leakage and interface traps in MOSCAP devices may be used in order to understand how these mechanisms affect more complex devices such as vertical GAN MOSFETs. GaN MOSFET and MOSCAP devices are often investigated and implemented in power systems with applications ranging from electric vehicles (EVs) to smart power grids. The unique material properties of GaN such as wide bandgap, high breakdown voltage, and high electron mobility create unique advantages over traditional silicon FETs. Vertical GAN MOSFETs are better suited for higher voltage applications due to current flow and voltage drop perpendicular to the surface while also reducing required chip area for high operating voltages. Although there are many advantages of vertical GaN devices, such an architecture presents unique challenges that must be addressed before such devices may be implemented in high power applications, such as the requirement for a native substrate and the need to improve the gate dielectric interface. The interface between the gate dielectric and the semiconductor is crucial in order to reduce threshold voltage drift, leakage current, and the density charge traps. Previous work has shown the importance of DIT reduction with chemical cleans and PDAs. Accurate calculations of the density of interface traps (DIT) are vital to fully realize device operation and reliability. The choice between surface cleans and dielectric annealing as a leakage reduction technique is dependent on the material and available processing capabilities. While PDAs may reduce the dielectric breakdown strength, they have been found to reduce gate leakage current and improve device performance for most gate dielectrics. Several methods have been proposed for DIT characterization, including the voltage dependencies of low- and highfrequency capacitance (CV), conductance (GV), and surface potential (WY). DIT may be calculated from the surface potential of the dielectric using the quasi-static capacitance and the capacitance of the chosen gate dielectric. This work uses quasi-static CV and surface potential electrical characterization of GAN MOSCAPs to determine DIT of various gate dielectric materials treated with PDAs and chemical cleans. Optimization of such films on MOSCAPs will allow for implementation into vertical GAN MOSFET architectures. Interface trap density may be reduced by decreasing the capacitance associated with defects and surface contamination or by selection of a dielectric material with a lower dielectric constant. Fixed charges at the dielectric/semiconductor interface are manifested in hysteresis between forward and reverse voltage sweeps and may be the result of contamination prior to ALD or point defects in the material. Al,0. is an attractive gate dielectric material due to its dielectric constant, which may improve breakdown strength (Fig. 1), but it may suffer from higher memory charge between continuous bias sweeps. SiO, ALD films have lower breakdown and significantly lower leakage currents but show the lowest density of remaining fixed charges between sweeps, suggestive of the lowest DIT of the tested dielectrics (Fig. 2) with the addition of PDA. Results were verified by altering bias conditions during testing in order to accumulate and deplete interface charges. Minor plateaus in capacitance in forward bias indicate the presence of negative fixed interface charges. Additional characterization may be necessary to determine the optimal conditions for DIT reduction for HfO., films, including reduction in PDA temperatures in combination with improved substrate chemical cleans.

Gallium Nitride (GaN) and its alloys form a promising material system for optoelectronic and electronic devices. Heteroepitaxial growth of GaN on sapphire and SiC, while viable, introduces threading dislocations (between 1E8 – 1E11 cm^-2), mismatches in thermal expansion coefficients, and limitations on available growth orientations other than the polar, <0001> directions. With a push towards longer wavelengths, higher output powers at higher efficiencies with reduced droop for LEDs, non-polar and semi-polar oriented devices are becoming increasingly important, though need currently lacking, large area, bulk GaN substrates. A solution is the ammonothermal growth technique, which entails dissolving a GaN feedstock in a supercritical ammonia solution containing sodium (P < 270 MPa, T = 500–600 °C) and re-crystallizing the material on a GaN seed. Improvements in growth rate are needed to reduce cost and increase throughput. To that end, an ultra high purity (UHP) growth environment was created within a typical Ni-Cr superalloy autoclave by introducing a silver capsule. 40 basic ammonothermal growth runs were performed on hydride vapor phase epitaxy (HVPE) GaN seed crystals. The capsule design significantly reduced concentrations of transition metals in the GaN crystals (<1x1E17 cm^-3) while improving the transparency to α(450 nm) = 2.2 cm^-1. Total growth rates improved from 200 to 344130 μm/day for c-plane and from 34 to 4612 μm/day for m-plane growth. Degradation in crystal quality based on the full width at half maximum of the ω-rocking curve using X-ray diffraction when compared to the seed crystal was only observed for Ga-face growth on c-plane oriented seeds, presumably due to poor nucleation. Cracking in thick growth layers was observed due to strain originating from the HVPE seed crystals. Differences in the total system pressure profiles were analyzed and the observed pressure drop due to outward diffusion of hydrogen during growth was modeled.

Dynamic ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}{)}$ </tex-math></inline-formula> or threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}{)}$ </tex-math></inline-formula> instability caused by charge trapping is one of the most crucial reliability concerns of some gallium nitride (GaN) high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {ON}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> stability of an industrial vertical GaN transistor-NexGen’s 1200-V/70- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> fin-channel junction-gate field-effect transistor (JFET), fabricated on 100-mm bulk GaN substrates. A circuit setup is deployed for the in situ measurement of the dynamic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}$ </tex-math></inline-formula> under steady-state switching. The longer term stability of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}$ </tex-math></inline-formula> or <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}$ </tex-math></inline-formula> -field) crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices toward power electronics applications.

In this work, we report fabrication and characterization of high breakdown voltage and high current injection vertical gallium nitride (GaN)-on-GaN p-n diodes with an etched mesa structure with guard rings termination on ammonothermally grown bulk GaN substrates. Bright electroluminescence from active region under forward bias was observed with high intensity near band edge emission and low intensity defect and unintentional impurities-related bands. Fabricated devices were characterized by a high breakdown voltage up to 1940 V, a high on/off current ratio over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{13}}$ </tex-math></inline-formula> , a high current density above 10 kA/cm2, and an extremely low ON-resistance below 0.1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> cm2 under high current injection.

Gallium nitride (GaN) possesses remarkable characteristics such as a wide bandgap, high critical electric field, robust antiradiation properties, and a high saturation velocity for high-power devices. These attributes position GaN as a pivotal material for the development of power devices. Among the various GaN-based devices, vertical GaN MOSFETs stand out for their numerous advantages over their silicon MOSFET counterparts. These advantages encompass high-power device applications. This review provides a concise overview of their significance and explores their distinctive architectures. Additionally, it delves into the advantages of vertical GaN MOSFETs and highlights their recent advancements. In conclusion, the review addresses methods to enhance the breakdown voltage of vertical GaN devices. This comprehensive perspective underscores the pivotal role of vertical GaN MOSFETs in the realm of power electronics and their continual progress.

Vertical gallium nitride (GaN) power devices have attracted increased attention due to their superior high-voltage and high-current capacity as well as easier thermal management than lateral GaN high electron mobility transistors. Vertical GaN devices are promising candidates for next-generation power electronics in electric vehicles, data centers, smart grids and renewable energy process. The use of low-cost foreign substrates such as silicon (Si) substrates, instead of the expensive free-standing GaN substrates, could greatly trim material cost and enable large-diameter wafer processing while maintaining high device performance. This review illustrates recent progress in material epitaxy, device design, device physics and processing technologies for the development of vertical GaN power devices on low-cost foreign substrates. Although the device technologies are still at the early stage of development, state-of-the-art vertical GaN-on-Si power diodes have already shown superior Baliga’s figure of merit than commercial SiC and Si power devices at the voltage classes beyond 600 V. Furthermore, we unveil the design space of vertical GaN power devices on native and different foreign substrates, from the analysis of the impact of dislocation and defects on device performance. We conclude by identifying the application space, current challenges and exciting research opportunities in this very dynamic research field.

Wide bandgap electronics made from nitrides (e.g., Gallium Nitride (GaN)) and oxides (e.g., Gallium Oxide (Ga2O3)) are currently under development due to their potential to create some of the most advanced RF and power electronic devices in the world. However, the thermal response of these devices under applied electric fields can create large power densities (RF and power electronics) that must be understood. For many of these devices, the electrothermal response plays a strong role in both the acceptable operation or long-term failure and reliability of the devices. Thus, tools that can help elucidate these responses and provide a method to help design better devices is of critical need for this field.In this talk we will discuss advancements in thermal characterization techniques that have allowed new insights into electrothermal behavior in GaN and Ga2O3 materials and devices. Specifically, a focus on the role of device architecture and material processing will be addressed. For GaN and Ga2O3 RF and power electronics, the role of thermal interfaces in the heat dissipation of both lateral and vertical device architectures will be discussed. We will cover aspects of semiconductor-semiconductor as well as metal-semiconductor interfaces and their roles in device thermal management. A highlight will be the use of plasma activated bonding to provide ultralow thermal resistance interfaces that allow for heterogenous integration of nitrides and oxides with high thermal conductivity substrates. Finally, we will discuss the implications of these effects on device behavior through experiments and modeling.

The surface and growth conditions for the formation of textured polycrystalline bulk gallium nitride (GaN) crystals under nitrogen (N2) reactive plasma were investigated. Langmuir probe measurements were used to determine the electron density values near the Ga surface at different target locations and ranged from (6–16)×1010/cm2. Optical spectroscopy measurements showed reactive gallium (Ga) and nitrogen species present in the plasma. When the target was bombarded with highly energetic ions, peaks of sputtered Ga at 403 and 417 nm wavelengths were observed in the optical spectroscopy measurements. The top Ga surface showed increased roughening and the resulting crystals were of poor crystalline quality, with fresh Ga leftovers. Smoother crystals were formed when the Ga target was shielded from the direct bombardment of highly energetic N2 plasma, with no sputtered Ga peaks observed during the bombardment. X-ray diffraction (XRD) analysis results revealed well-oriented crystals at the (0002) reflection of GaN. This proved that the shielding of highly energetic ions to decrease roughening of the surface and allowing more neutrals for the reaction were effective in forming well-oriented bulk GaN crystals.

Design considerations for vertical Gallium Nitride (GaN) nanowire Schottky barrier diodes (NWSBDs) for high voltage applications is discussed in this paper. Preliminary quasi-vertical NWSBDs fabricated on a Sapphire substrate show rectifying properties with breakdown voltage of 100 V. The principle of dielectric Reduced SURface Field (RESURF) which is naturally compatible with the NW structure, is utilized to block high voltages (> 600 V) within the fabrication constraints of nano-pillar height and drift doping concentration. Design considerations for the NWSBD is explored through 3D TCAD simulations. TCAD simulations show the NWSBDs can block voltages upward of 700 V with very low on-resistance with optimal design. The measured and simulated results are compared with state of the art GaN devices to provide an understanding of the true potential of the GaN NW architecture as power devices offering high breakdown voltages and low on-state resistance and a reliable device operation, all on a vertical architecture and a non-native substrate.

Power semiconductor devices, spanning blocking voltages from a few volts to tens of thousands of volts, are critical for efficient energy conversion in numerous applications and serve as key enablers of carbon neutrality. These devices can be realized in either vertical or lateral architectures, with the former preferred for high-power discrete devices and the latter offering high switching speeds and monolithic circuit integration. While lateral structures have long been utilized in low- and medium-voltage applications, recent advancements in multidimensional device architectures and (ultra-)wide-bandgap semiconductor materials have revitalized their potential for high-voltage applications. Multidimensional architectures, such as superjunction and multichannel designs, enable uniform electric field distribution for voltage scaling and, at the same time, boost carrier concentrations to enhance current capacity. The application of these architectures in gallium nitride and gallium oxide has led to the demonstration of multi-kilovolt lateral devices with diverse designs, achieving breakdown voltages exceeding 10 000 V, average electric fields up to 4.7 MV/cm, high-temperature operation up to 250 °C, and specific on-resistances at least 2–3 times lower than similarly rated vertical devices. Such advantages can be further enhanced through the implementation of monolithic bidirectional devices, a unique capability of the lateral architecture that enables the replacement of four vertical devices. This review provides an overview of multidimensional high-voltage lateral devices, emphasizing their fundamental device physics to inspire further applications across various material systems. The theoretical performance limits of multidimensional lateral devices are also analyzed. In addition, we discuss critical knowledge gaps that must be addressed for industrial adoption, highlighting emerging research opportunities in this rapidly evolving field.

This article studies the switching performance of vertical GaN power FinFETs and proposes new interfin designs to improve it. The interfin region has been found to be an important limiting factor for FinFET switching performance. The time taken to (dis)charge the dielectric parasitic capacitances and drift layer in the interfin regions severely limits the device turn-(on)off speed. Three new interfin designs are proposed, based on reduced fin-to-fin spacing, oxide full-filling (FF), and split-gate (SG) structures. The 1.2-kV, 80-mΩ vertical GaN FinFETs with these designs were evaluated by a well-calibrated device-circuit mixed-mode technology computer-aided design (TCAD) simulation. Both the reduced-fin-spacing structure and the oxide FF reduce the dielectric parasitic capacitances, but only lead to small reduction (less than 10%) in switching losses. Much better improvement is obtained with the SG structure, which removes the gate metal in the interfin region and exposes the drift layer to the field lines from the source metal. During the turn-(on)off of the transistor with a SG structure, the drift layer underneath the interfin gap region is (dis)charged by a combination of the drain-to-source and gate currents, leading to shorter switching times and lower switching losses. By utilizing the SG structure, simulations predict a 58% improvement in the switching figure-of-merit and 38% lower switching losses in 1.2-kV vertical gallium nitride (GaN) power FinFETs. These results provide key understanding and design guidelines for power FinFETs. Finally, an 800-V buck converter using a 1.2-kV GaN FinFET half-bridge module is simulated, showing excellent efficiency when operating at a multi-MHz frequency and revealing the requirement for device thermal management. This highlights the great potential of vertical GaN power FinFETs for future high-frequency medium-voltage power applications.

Vertical silicon carbide transistors and lateral gallium nitride (GaN) transistors for power‐electronic applications currently target applications with different voltage and power ratings. Meanwhile, research and development activities continue on vertical GaN transistors and new gallium oxide (Ga2O3) transistors. What are their perspectives in the application and how do they compete against each other and against established transistor technologies? This study discusses the specific characteristics of lateral and vertical GaN and Ga2O3 transistors to assess their strengths and weaknesses.

Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices.

Increasing the power density of PV inverters have been of great interest in the PV industry. With a smaller and lighter inverter, the installation cost can be greatly reduced, making solar energy more affordable. To improve the power density of PV inverters, a new internal parallel converter has been proposed in the literature and prototyped. This paper presents the key design considerations of the Gallium Nitride (GaN) based power stage as the high switching frequency (HSF) module in the modularized prototype. Two issues have been addressed in detail, i.e. the sizing of film capacitor based flying capacitor (FC) and design of GaN power board. A current stress based sizing has been investigated for FC indicating that the volume of the FC bank is dominated by the current stress instead of the switching frequency. Furthermore, design of the GaN power board based on insulated metal substrate (IMS) board has been discussed in detail. In addition to improved thermal performance, the metal substrate can serve as a shielding layer and help reducing the power loop parasitic inductance. Experimental results have confirmed that the designed GaN HSF module can safely operate under full power.

Synthesis of gallium nitride by ammonia injection into gallium melt