Power invariant secure IC design methodology using reduced complementary dynamic and differential logic

Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards against power analysis attacks

Low-power secure applications such as Radio Frequency IDentification (RFID) and smart cards represent extremely constrained environments in terms of power consumption and die area. This paper investigates the power, delay and security performances of the dynamic differential swing limited logic (DDSLL). A complete analysis of an advanced encryption standard (AES) S-box is conducted using a low-power (LP) 65 nm CMOS technology node. Measurements show that the DDSLL S-box has 35% less power consumption than the static CMOS S-box, with an area increase of only 12%, at the expense of a 2.5× increase in delay which remains fairly acceptable for low-power applications such as RFIDs and smart cards. Also when compared to other dynamic differential logic (DDL) styles, simulation results show that DDSLL and dynamic current mode logic (DyCML) consume the same power which is about 1.8× less that of sense amplifier based logic (SABL). The effect of process variations is also studied, measurement results show that the DDSLL style has lower variability in terms of dynamic power as the activity factor (αF) is deterministic thanks to glitch-free operation. As for security, the perceived information metric demonstrates that the DDSLL S-box has a 3× security margin compared to static CMOS. Therefore, DDSLL presents an interesting tradeoff between improved security and area constrained low-power designs.

Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential Power Analysis (DPA) is a type of SCA, which exploits the device's power consumption characteristics. Several countermeasures to DPA have been proposed, however, all of them increase security at the cost of increased area which in-turn leads to increased power consumption and reduced throughput. FPGAs are popular due to their reconfigurability, lower development cost, off-the-shelf availability and shorter time to market. Block RAMs (BRAM) are large memories in FPGAs that are commonly used as ROM, FIFO, Look-up tables, etc. In this paper we explore the DPA resistance of BRAMs in Xilinx FPGAs and verify if their usage can improve the security. The results of our Advanced Encryption Standard (AES) implementations show that using BRAMs alone can improve the security over a look-up table (LUT) only design 9 times. Applying Separated Dynamic Differential Logic (SDDL) for FPGAs, a countermeasure against DPA, to this design doubles the security again leading to an 18 fold increase over the unprotected LUT design.

Side channel attacks (SCAs) exploit the fact that security IC physical implementation of a cryptographic algorithm can leak information of the secret key. One of the most important SCA is Differential Power Analysis (DPA), that uses the power consumption dependence with the data processed to reveal critical information. To protect security devices against this issue, differential logic styles with constant power dissipation have been widely used. However, the right use of such circuits for secure applications needs not only a fully symmetric structure, but also removing any memory effect that could leak information. We propose an improved memory-less fully symmetric Xor/Xnor pull-down logic configuration, to be used with any differential technique, for immediate application in crypto-graphic secure applications.

In this paper we propose a differential dynamic dual rail CMOS logic style for ultra-low-voltage and high-speed operation. For a supply voltage equal to 300mV using a 90nm TSMC CMOS process the delay of the proposed logic style is reduced more than 96% compared to the delay of dual rail clocked voltage switch logic.

Wave Dynamic Differential Logic (WDDL) is a hiding countermeasure to thrawt side channel attacks (SCA). It suffers from a vulnerability called Early Evaluation, i.e. calculating output before all inputs are valid. This causes delay biases in WDDL even when synthesized with positive gates. s a consequence, the design can be attacked, although with extra effort, through side channel. However, WDDL is an appealing logic since it has already been reported to natively resist against multiple asymmetric faults. In this article, we suggest a Dual Rail Precharge Logic (DPL), similar to WDDL, free from early evaluation by design. We demonstrate practically that the early evaluation accounts for major part of the leakage. We also provide basic guidelines for designing such a DPL. This DPL can resist against side channel attacks and fault attacks at the same time. In line with the current security evaluation methodology, we use differential power analysis and mutual information to compare the modified WDDL with the traditional WDDL. To compare robustness w.r.t security, we conduct a proof-of-concept experiment that compares the two logics with identical implementations (P&R) apart from the logic style. The sensitive side channel leakage is reduced by half in the DPL without the early evaluation flaw.

Differential power analysis (DPA) has been shown to be an effective attack on cryptographic systems capable of releaving secret data by measuring power consumption. DPA resistant circuits currently experience severe problems in terms of performance, area, and power. Although different countermeasures to reduce DPA attacks have been proposed and implemented in general, such protections do not make attacks infeasible. Additionally, most are dual rail logic families, Delay Based Dual Rail Precharge Logic (DDPL) with high resistance is presented and significantly lower overheads in performance, area, and power than other DPA resistant logic styles. The Delay Based Dual Rail Precharge Logic (DDPL) shows a certain improvement in Normalized Energy Deviation(NED) with respect to other dual rail logics.

Since the vulnerability of cryptosystems to differential power analysis (DPA) was reported in 1999, various power analysis attacks and corresponding countermeasures have been studied. With the scaling down of supply voltage and CMOS technology below 90 nm, leakage power plays an increasing role in the overall power dissipation. Future cryptosystems need to address this trend, though it has not been of concern yet in low- cost cryptosystems such as smartcards and RFED tags which currently use older technologies and low performance transistors. In this paper, we explore the impact of leakage power on conventional DPA and the feasibility of a novel leakage-based DPA (LDPA). We first use SPICE simulations to explore the leakage dependence on input patterns of logic gates implemented in 90 nm, 65 nm, and 45 nm CMOS technologies. Then we simulate a successful LDPA on a subset of a DES cryptosystem with only 120 rounds, in contrast to the 200 rounds reported for a conventional DPA in 180 nm technology. Furthermore, we demonstrate how even a DES implementation using a DPA-resistant logic style can be broken with LDPA in 2000 rounds, compared with the conventional DPA using more than 5000 rounds.

Physical Unclonable Functions (PUFs) provide a cost-efficient way to store a secure key on a device. But the noisy secret from a PUF must be corrected to generate a stable key. Since the error correction processes secret material, it is a target of attacks. Previous work has shown that single bits of a key can be extracted using a power side-channel attacks. This work enhances the attack idea. Non-invasive measurement of electromagnetic radiation together with a differential power analysis is shown to be sufficient to extract not only single bits but even the complete key from an error correction used for PUF-based key generation. The efficiency of the basic attack is significantly improved over state of the art using public available preknowledge on the PUF, an advanced correlation method, and parallel manipulation of helper data. The attack is practically demonstrated on an FPGA implementation with concatenated BCH and repetition codes. The results show that, compared to state of the art, a significant improvement by a factor of more than 100 in terms of trace reduction can be achieved.

We investigate our previously proposed charge sharing symmetric adiabatic logic, which was designed to thwart differential power analysis (DPA) attack. The ability of the logic to withstand DPA attacks is analyzed from the variations in the transitional power consumption of individual logics and in the bit-parallel cellular multiplier over GF(2m). Then, we compare the results with those of the previous secure logic styles using the same parameters and under the same conditions. Based on the simulated program with integrated circuit emphasis (SPICE) simulation results, we deduce that our proposed logic is a suitable candidate for secure hardware application in the low-power and low-frequency fields, such as contactless smart card, RFID tags, and wireless sensors.

The 128-bit SM4[1] cipher is the first commercial cipher algorithm published by China in 2012, which is mainly used in WLAN. Comparing with conventional approaches, additive masking is adopted to resist the DPA (Differential Power Analysis) attack, and PPRM circuit structure is adopted to reduce the power consumption for SM4 S-box. Simulation results show that the design has a 50% reduction in power consumption and a 44% reduction in delay at the cost of area 20% increased using SMIC 0.18μm technology. Two sets of 2000 plaintext inputs are used in the DPA attack. Simulation results show the resistance of S-box to DPA is reliable. Additionally, 4-stage-pipelined SM4 cipher circuit is realized with an area of 18609 gates. The throughput rate of it can reach 2Gbps with a power consumption of 3.65mW@10Mhz.

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key’s corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace

Differential Power Analysis (DPA) aims at revealing secret keys in cryptographic devices by analyzing their power consumption as side-channel information. Although power consumption models based on transition probability were used to evaluate a DPA-resistance in previous studies, the adequacy of this model has not been confirmed enough. In this paper, we show two experiments about information of power consumption precisely, and show that Random Switching Logic which is one of the DPA-countermeasures is in reality not secure against DPA.

Cryptography is securing information using mathematical techniques like encryption and decryption. Cryptanalysis uses side-channel attacks to undermine security. The efficient type of power analysis of the side channel and Differential Power Analysis (DPA) statistically assesses the power use of the cryptographic method and provides private details. This paper proposes the design of a Compact PRESENT S-box (CPSB), using Three-Phase Dual Rail Pre-Charge Logic (TDPL) combined with Charge Balancing Symmetric Pre-Resolve Adiabatic Logic (CBSPAL). The primary contribution of this research lies in the development of a power-efficient logic style that improves the performance of the S-box while maintaining conflict against DPA attacks. By employing TDPL, the design achieves consistent power consumption across various input configurations, thereby mitigating the risk of side-channel attacks. The focus of this work is to propose an innovative implementation approach rather than the security aspects of cryptography itself. The proposed methodology proves a substantial reduction in power overhead and area, making it suitable for resource-constrained environments, like Internet of Things (IoT) applications. A correlation study is carried out to calculate the Compact Present S-box implementation's DPA resistance characteristic. The power traces are examined. The proposed design makes power consumption consistent and decreases area and power overhead by 15.3% and 13.6%, respectively. Performance indicators for the security are NED, NSD, and Pearson correlation coefficient. The connection is the same for all conceivable input and key pairings. When compared with other designs, the NED and NSD were determined to be 0.02% and 0.01%, respectively.

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