Power reduction of multiple disks using dynamic cache resizing and speed control

Introduction. The article discusses the problem of improving the efficiency and safety of urban transport systems through the introduction of dynamic speed control. The relevance of the study is due to the need to adapt traffic parameters in real time to changing road and weather conditions. The work analyzes the evolution from classical traffic control systems to advanced systems integrated into intelligent transport systems (ITS). Particular attention is paid to dynamic speed control methods using variable information display (VMI) and the prospects for the introduction of infrastructure-vehicle (V2I) communication technologies. Materials and methods . The main research method is simulation modeling in Aimsun using the example of the Kazan street and road network. 12 strategies for zonal speed control (from 20 to 80 km/h) were developed and their comparative analysis was carried out by means of meso- and micromodeling methods for the morning peak period. Results. It has been shown that differentiated control has an effective impact on the flow parameters. The best results were demonstrated by the C3 Strategy (limits of 80, 60, 60 km/h by zone), ensuring the minimum total time spent (769,253 seconds), maximum average speed (35.33 km/h) and throughput (35,566.5 T/h). Strategies with uniformly low constraints resulted in deteriorated indicators. Discussion and conclusion. The conducted research confirms the high efficiency of dynamic zonal speed control for optimizing traffic flows in urban conditions. It has been established that differentiated regulation (rather than a single strict restriction) makes it possible to find a balance between bandwidth, speed of movement and the level of network load. The best results have been shown by the C3 Strategy, which assumes relatively high speed limits on main routes. Further research will provide increased control efficiency associated with the integration of V2I technologies to allow for individual and continuous speed control for each vehicle, which will lead to further harmonization of traffic flow and increased safety.

Improving memory energy consumption of programs that manipulate arrays is an important problem as these codes spend large amounts of energy in accessing off-chip memory. We propose a data-driven strategy to optimize the memory energy consumption in a banked memory system. Our compiler-based strategy modifies the original execution order of loop iterations in array-dominated applications to increase the length of the time period(s) in which memory banks are idle (i.e., not accessed by any loop iteration). To achieve this, it first classifies loop iterations according to their bank accesses patterns and then, with the help of a polyhedral tool, tries to bring the iterations with similar bank access patterns close together. Increasing the idle periods of memory banks brings two major benefits: first, it allows us to place more memory banks into low-power operating modes and, second, it enables us to use a more aggressive (i.e., more energy saving) operating mode (hence, saving more energy) for a given bank (instead of a less aggressive mode). The proposed strategy can reduce memory energy consumption in both sequential and parallel applications. Our strategy has been implemented in an experimental compiler using a polyhedral tool and evaluated using nine array-dominated applications on both a cacheless system and a system with cache memory. Our experimental results indicate that the proposed strategy is very successful in reducing the memory system energy and improves the memory energy by as much as 36.8 percent over a strategy that uses low-power modes without optimizing data access pattern. Our results also show that optimizations that target reducing off-chip memory energy can generate very different results from those that target at improving only cache locality.

The demand for higher computing power and, thus, more on-chip computing resources; is ever increasing. The size of on-chip cache memory has also been consistently increasing to keep up with developments in implementation technology. However, some applications may not utilize full cache capacity and, on the contrary, require more computing resources. To efficiently utilize silicon real-estate on the chip, we exploit the possibility of using a part of cache memory for computational purposes to strike a balance in the usage of memory and computing resources for various applications. In an earlier part of our work, the idea of adaptive balanced computing (ABC) architecture was evolved, where a module of an L1 data cache is used as a coprocessor controlled by main processor. A part of an L1 data cache is designed as a reconfigurable functional cache (RFC) that can be configured to perform a selective core function in the media application whenever such computing capability is required. ABC architecture provides speedups ranging from 1.04x to 5.0x for various media applications. We show that a reduced number of cache accesses and lesser utilization of other on-chip resources, due to a significant reduction in execution time of application, will result in power savings. For this purpose, we first develops a model to compute the power consumed by the RFC while accelerating the computation of multimedia applications. The results show that up to a 60 percent reduction in power consumption is achieved for MPEG decoding and a reduction in the range of 10 to 20 percent for various other multimedia applications. Besides, beyond the discussions in earlier work on ABC architecture, we present a detailed circuit level implementation of the core functions in the RFC modules. Further, we go much further and study the impact of converting the conventional cache into RFC on both access time and energy consumption. The analysis is performed on a wide spectrum of cache organizations with size varying from 8KB to 256KB for varying set associativity.

Cache memory plays an important role in high speed electronic devices. SRAM is the key element of cache memory. Cache memory is used for their high speed and SRAM is the element which provides speed to the cache. So this work is mainly concentrated on the simulation and analysis of 8T SRAM cells and their comparative analysis of different parameters such as width to length ratio, capacitance and power consumption. All the simulation has been carried out using Microwind and DSCH2 EDA tool.

Cache memories are an indispensable component of many processor-based systems and contribute significantly to the overall area, power consumption, and delay. This leads to an important role played by modeling tools for estimating the area, power consumption, and access time of cache memories. However, existing modeling tools such as CACTI and its various extensions have been primarily designed using data from various projections. For the first time, we propose an entire flow for obtaining/calibrating the transistor characteristics from a commercial technology and use these characteristics within CACTI. We also improve the modeling approach to make them more fine-grained and follow recent manufacturing trends suitable for FinFET technology. Further, for the first time, we extend CACTI to support negative capacitance fin field effect transistor (NC-FinFET), an emerging technology depicting negative capacitance whose current and capacitive characteristics are very different compared to those of the FinFET. We use the proposed tool (FN-CACTI) to identify NC-FinFET-based caches to be significantly more energy-efficient than corresponding FinFET-based caches. We also study an application of FN-CACTI to determine optimal voltages corresponding to the lowest energy consumption for NC-FinFET and FinFET-based caches of various sizes.

Many authors have proposed power management techniques for general-purpose processors at the cost of degraded performance such as lower IPC or longer delay. Some proposals have focused on cache memories because they consume a significant fraction of total microprocessor power. We propose a reconfigurable and adaptive cache microarchitecture based on field-programmable technology that is intended to deliver high performance at low energy consumption. In this paper, we evaluate the performance and energy consumption of a run-time algorithm when used to manage a field-programmable L1 data cache. The adaptation strategy is based on two techniques: a learning process provides the best cache configuration for each program phase, and a recognition process detects program phase changes by using data working-set signatures to activate a low-overhead reconfiguration mechanism. Our proposals achieve performance improvement and cache energy saving at the same time. Considering a design scenario driven by performance constraints, we show that processor execution time and cache energy consumption can be reduced on average by 15.2% and 9.9% compared to a non-adaptive high-performance microarchitecture. Alternatively, when energy saving is prioritized and considering a non-adaptive energy-efficient microarchitecture as baseline, cache energy and processor execution time are reduced on average by 46.7% and 9.4% respectively. In addition to comparing to conventional microarchitectures, we show that the proposed microarchitecture achieves better performance and more cache energy reduction than other configurable caches.

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

By integrating multiple cores in a single chip, Chip Multiprocessors (CMP) provide an attractive approach to improve both system throughput and efficiency. This integration allows the sharing of on-chip resources which may lead to destructive interference between the executing workloads. Memorysubsystem is an important shared resource that contributes significantly to the overall throughput and power consumption. In order to prevent destructive interference, the cache capacity and memory bandwidth requirements of the last level cache have to be controlled. While previously proposed schemes focus on resource sharing within a chip, we explore additional possibilities both inside and outside a single chip. We propose a dynamic memory-subsystem resource management scheme that considers both cache capacity and memory bandwidth contention in large multi-chip CMP systems. Our approach uses low overhead, non-invasive resource profilers that are based on Mattson's stack distance algorithm to project each core's resource requirements and guide our cache partitioning algorithms. Our bandwidth-aware algorithm seeks for throughput optimizations among multiple chips by migrating workloads from the most resource-overcommitted chips to the ones with more available resources. Use of bandwidth as a criterion results in an overall 18% reduction in memory bandwidth along with a 7.9% reduction in miss rate, compared to existing resource management schemes. Using a cycle-accurate full system simulator, our approach achieved an average improvement of 8.5% on throughput.

Cache memories are an important component of modern processors and consume a large percentage of the processor’s power consumption. The quality of service of this cache memories relies heavily on the memory demands of the software, what means that a certain program might benefit more from a certain cache configuration which is highly inefficient for another program. Moreover, finding the optimal cache configuration for a certain program is not a trivial task and usually, involves exhaustive simulation. In this paper, we propose a machine learning-based methodology that, given an unknown application as input, it outputs a prediction of the optimal cache reconfiguration for that application, regarding energy consumption and performance. We evaluated our methodology using a large benchmark suite, and our results show a 99.8% precision at predicting the optimal cache configuration for a program. Furthermore, further analysis of the results indicates that 85% of the mispredictions produce only up to a 10% increase in energy consumption in comparison to the optimal energy consumption.

A microprocessor is as secure as its weakest module. Depending on the application, the weakest module may be present in the hardware, micro-architecture, or a vulnerability in the software. For instance in a web-server, the biggest threats occur due to software vulnerabilities and due to information leakage in shared micro-architecture components. On the other hand, in an end-point IoT device, invasive and non-invasive hardware attacks such as Differential Power Analysis (DPA), are arguably the biggest threats. In this paper we highlight some aspects of the development of a secure processor called Shakti-S. The processor is configurable and can cater to vulnerabilities in multiple layers. To protect against memory vulnerabilities that are common in applications, hardware enabled memory protection schemes are implemented. Fine-grained compartment capabilities permit the secure least-privilege software design methodology. In the micro-architecture, shared modules like cache memories are protected by moving target randomization mechanisms which can prevent most variants of cache timing attacks. In the hard-ware, critical information is masked to break correlation with the device’s power consumption, thus hardening the processor against strong side-channel attacks like the Differential Power Analysis.

Objective: Technology trend are one of the most important to use the bulky on-chip memories such as level-2 (L2) and level-3 (L3) cache. In this paper, Non-Uniform Cache access Architectures (NUCA) has been used in order to decrease the effects of the high access latencies. For the systems which operate at high frequency, the latencies of such caches are conquered by wire delays. Methods: In this architecture, several banks are partitioned and which is connected to the controller through switches and links. This larger cache memory increases overall wire delays across the chip due to very bulky latencies. The majority of the access time will not absorb them self and that occupy in the routing to and from the several banks. The predictable lower-level caches have the best ever access time among the entire the sub arrays, although such uniform cache access don’t make the use of differences in latencies of the entire sub arrays. Findings: Hence there is a necessitate for non-uniform cache architectures where the cache memories is broken down into several banks that can be analyzed at dissimilar latencies and resulting in diminish of energy and power consumption. Applications/ Improvements: An experimental result shows the comparison of NUCA and UCA using SRAM/MRAM in terms of power and energy Keywords: Chip Multiprocessors, Non Uniform Cache Access, Uniform Access

Increasing the security of memory systems is relevant due to the sensitive information which is stored in plain-text. Over the last decade, device specific attacks have been reported as being successfully in retrieving encryption and private keys from AES algorithms. A novel technique is proposed in this work, which improves the security of a cache memory through the use of data scrambling. Several dissemination rules are explained and employed, in order to make the proposed method a viable security solution. The proposed technique is evaluated from several points of view (area overhead, power consumption and performance) and compared to a standard technique.

SRAM is the key element used in digital circuits. It is also used as a cache memory in computers, automatic modern equipment like mobile phones, modern appliances, digital calculators, digital cameras, so that the requirements of high-speed advanced memory or embedded memory lead to the development of low-voltage SRAMs. The paper has introduced the design and simulation of the distinctive source-based sense amplifier which is a peripheral circuit for static random access memory (SRAM) that has to amplify the data which is present on the bit lines during the read operation. Simulation of the proposed design has been implemented using 20 nm FinFET technology on the Cadence Virtuoso Tool with a supply voltage of +0.4 V. The main advantages from the proposed design circuit are less power consumption and display of minimum sense delay in sensing the data from SRAM when compared to the existing design circuit. A comparison is drawn between the proposed circuit and the existing design circuit.

Dynamic cache resizing coupled with Built In Self Test (BIST) is proposed to enhance yield of SRAM-based cache memory. BIST is used as part of the power-up sequence to identify the faulty memory addresses. Logic is added to prevent access to the identified locations, effectively reducing the cache size. Cache resizing approach can solve for as many faulty locations as the end user would like, while trading off on performance. Reliability and long term effect on memory such as pMOS NBTI issue is also compensated for by running BIST and implementing cache resizing architecture, hence detecting faults introduced over time. Since memory soft failures are worst at lower voltage operation dynamic cache resizing can be used to tradeoff power for performance. This approach supplements existing design time optimizations and adaptive design techniques used to enhance memory yield. Performance loss incurred due to the cache reduction is determined to be within 1%.

A dynamic temporal and spatial speed control strategy for partially connected automated vehicles at a signalized arterial