Precise realisation of current mode integrator using current conveyor

A new single-element-controlled sinusoidal oscillator circuit that incorporates two second generation current conveyors (CCIIs), two grounded capacitors and two resistors is presented and analysed. The circuit is beneficial to monolithic integrated circuit implementation by the use of grounded capacitors. In addition, a new current-controlled sinusoidal oscillator using only two second generation current controlled conveyors (CCCIIs) and two grounded capacitors can be achieved by replacing CCIIs and resistors series at X terminals with CCCIIs. The oscillators provide extremely low passive ω0-sensitivities and good frequency stability. Moreover, the oscillation frequencies of the CCII-based and the CCCII-based oscillators can be controlled, respectively, by a grounded resistor and by an external bias current. Experimental and SPICE simulation results that confirm the theoretical predictions are given.

In this article, developments of Second Generation Current Conveyors (CCII) that are realized by based on the use of a differential amplifier (diff-amp) as a circuit building block are reviewed. The basic concepts of current conveyor are firstly outlined. One of the first CMOS-based promising techniques to implement CCII that proposed by Surakampontorn et al. is reviewed [9-11]. The applications of Surakampontorn’s CCII as basic circuit building blocks to realize analog circuits and systems and the modifications methods to provide multiple outputs CCIIs are outlined and discussed. Based on feedback mechanisms, diff-amp-based CCIIs that are designed by modified from the CCII are also outlined and discussed. In order to understand the improvement, the characteristics of the CCIIs that have been compared through simulation results by Hassanenin et al. [11] are presented. Finally, the concept of chemical current conveyor (CCCII) is also noted.

Active elements working in the current or mixed mode are still attractive for the design of analog functional blocks. The current conveyor (CC) was defined already in 1968. This paper deals with hysteresis comparators using second generation current conveyor. The comparator is basically a pulse circuit. In these circuits, the maximum rate of change in the output voltage is required during switching from one state to another. In comparators with operational amplifiers the switching time is given by the slew rate of the operational amplifier used, which is not too high. If a current conveyor is used, the time of switching the comparator gets shorter. The comparator is capable to operate at a higher frequency bands and if it is used, for example, in converters, a higher operating frequency can be reached. The connection of an inverting and a non-inverting comparator with adjustable hysteresis is shown as a practical implementation. Using the AD844, results of experimental measurements are presented that confirm the theoretical assumptions and the results of computer simulation.

In the field of analog VLSI design, current conveyors have reasonably established their identity as an important circuit design element. In the literature published during the past few years, numerous application have been reported which are based on a variety of current conveyors. In this paper, an oscillator circuit has been proposed. This oscillator is designed using a single positive type second generation current controlled current conveyor (CCCII+). A CCCII has parasitic input resistance on it’s current input node. This resistance could be exploited to reduce circuit complexities. Thus in this accord, a novel oscillator circuit is proposed which utilizes the parasitic resistance of the CCCII+ along with a few more passive components.

A new CMOS dual-X second generation current conveyor (DXCCII) with an FDNR circuit application

This paper presents two new single-resistance-controlled-oscillators (SRCOs), that employ a single first-generation current conveyor (CC) along with one/two voltage buffer(s) and a minimum of (five) passive components. Apart from providing noninteractive controls for both frequency of oscillation and condition of oscillation, a novel feature of these circuits is that they provide voltage-mode as well as currentmode outputs explicitly from the same structures, which is not available in any of the single-CC-based SRCOs published previously.

The (second generation) current conveyor is a building block that can be used to design linear circuits. Current conveyors have been used to design oscillators, filters and simulated inductors. This paper presents a simple procedure for analysing circuits that contain current conveyors. The procedure is well suited for manual calculations. It is also easily programmed and is compatible with a previously published algorithm for the computer analysis of linear networks. An important feature of the procedure is that it can be used to analyse networks containing non-ideal current conveyors.

Two new types of floating current conveyors are introduced. Each type has four ports: Y, X and two Z ports. The first type is the Floating Second Generation Current Conveyor (FCCII) and includes both CCII+ and CCII- as special cases. The second type is the Floating Inverting Second Generation Current Conveyor (FICCII) and includes both ICCII+ and ICCII- as special cases. The Nodal Admittance Matrix (NAM) stamp for the Nullator-Pathological Current Mirror is derived. Examples are given together with a CMOS circuit realizing both the FCCII and FICCII.

Recently, it has been shown by Paul-Dey-Patranabis that a floating NIC can be realized with two second generation current conveyors (CC), without constraints. In this communication it is shown that more useful floating generalized positive immittance converter/inverter elements too can be realized with only two second generation current conveyors.

A five-port general purpose analogue building block, termed as an operational floating current conveyor (OFCC), is described. The OFCC combines the features of a current feedback (CFB) operational amplifier, second generation current conveyor and operational floating conveyor (OFC). A simple implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working model. The OFCC is then used as a single block to realize the current conveyors (CCII+ and CCII-). Experimental results are presented and show good behavioral agreement with simulation results.

A new five-port general purpose analogue building block, termed as an operational floating current conveyor (OFCC), is described. The OFCC combines the features of current feedback (CFB) operational amplifier, second generation current conveyor and operational floating conveyor (OFC). A simple implementation scheme of the OFCC is described and its terminal operational characteristics are used to yield a working model. The OFCC is then used as a single block to realize the four main amplifier types and the current conveyors (CCII+ and CCII-). Computer simulation results are presented and discussed. >

We suggest circuit realizations of emulators transforming memristive devices into effective floating memcapacitive and meminductive systems. The emulator's circuits are based on second generation current conveyors and involve either four single-output or two dual-output current conveyors. The equations governing the resulting memcapactive and meminductive systems are presented.

In this paper, we propose method of generating grid multi-scroll chaotic attractors with the positive-type second generation current conveyors (CCII+). Firstly, a three-dimensional grid multi-scroll chaotic system is presented. Some basic dynamical properties are studied. Furthermore, we construct the saturation functions with current output and design the chaotic system with series structure by using current conveyers. In the whole design the port parasitic parameters of current conveyers are taken into considerations. By analyzing we could learn that the circuit can work in a higher frequency range. Finally, the effectiveness of this method is verified by circuit implementation.

Ant Colony Optimization (ACO) technique is more and more used by engineers and designers in order to optimally size their circuits/systems' performances. Despite the fact that ACO is robust and has a good intrinsic intensive research strategy, it suffers from its greedy requirement in computation time. In order to overcome this drawback, the BAcktracking Ant Colony Optimization (BA-ACO) has been successfully introduced to provide an adequate improvement to the ACO technique by integrating in this algorithm a backtracking search technique, thus reducing the computation time and substantially enhancing the convergence. Details of the BA-ACO algorithm are given in the following. An application to the optimal sizing of CMOS inverted second generation current conveyors (ICCII) is presented, and comparison results with published works are highlighted. SPICE simulation results are given to show the viability of the proposed algorithm.

This paper discusses bandwidth problems associated with second-generation current conveyors (CCII). In particular, our work is centered in high-capacitance applications, and has been oriented for wireless optical links and applied physics. We discuss techniques for improving bandwidth in these CCIIs, and develop a new CCII structure with larger bandwidth than traditional circuits. These circuits are then compared in terms of their noise and dynamic range characteristics. A test circuit was developed to verify these different bandwidth behaviors.