Predictability of image processing algorithms on heterogeneous MPSoC

The recent years have witnessed a variety of new embedded applications. Typical examples include mobile multimedia gadgets, digital televisions, high-end cell phones, wireless network applications, etc. The salient features of these applications include more comprehensive functionalities, higher performance demand, and low-power consumption. These requirements render the traditional single processor-based embedded systems no longer an appropriate realization for such applications. On the other hand, the continual advance of VLSI technologies enables more and more transistors to be integrated on a single chip. The International Technology Roadmap for Semiconductors predicts that chips with a billion transistors are within reach. As a result, the push (application demands) and pull (VLSI technology) forces together give birth to the multi-processor system-on-chips (MPSoCs).Heterogeneous MPSoCs are different from traditional embedded systems in many aspects and they ask for new design and implementation methodologies. Heterogeneous MPSoCs are not merely a hardware design. The complexity and heterogeneity of the system significantly increase the complexity of the HW/SW partitioning problem. Meanwhile, evaluating the performance and verifying its correctness is much more difficult compared to traditional single processor-based embedded systems. Constructing a simulator to simulate the system’s behavior and evaluate its performance takes more effort compared to conventional embedded systems. The verification of the system also becomes challenging.Programming a heterogeneous MPSoC is another challenge to be faced. This problem arises simply because there are multiple programmable processing elements and since they are heterogeneous, software designer needs to have expertise on all of these processing elements and needs to take a lot of care on how to make the software running as a whole.There are a lot more issues that do not appear or easier to tackle on traditional embedded systems, trade-offs between performance and low-power will dominate the design life time. However, the incoming challenges also brought us many opportunities either to industry and academic research.

Modern embedded applications keep getting more complex, while battery-powered platforms still face strict energy limits. This makes it crucial to design energy-efficient task mapping strategies for Network-on-Chip (NoC)-based heterogeneous Multi-Processor System-on-Chip (MPSoCs). To address this, we present a novel discrete optimization technique called the Binary Chimp Optimization Algorithm (BChOA). It is built to cut energy use when mapping multiple application tasks onto heterogeneous MPSoC architectures. BChOA takes the population behavior from the original Chimp Optimization Algorithm (ChOA) and modifies it to work more effectively with binary problems. It employs a sigmoid-based method to handle the transition from continuous to discrete, enabling it to search through the space of possible task-to-core assignments more effectively. We tested the effectiveness of BChOA by comparing it to three popular optimization methods: Particle Swarm Optimization (PSO), Genetic Algorithm (GA), and Ant Colony Optimisation (ACO). We ran all of them on standard application benchmarks like VOPD, MPEG-4, MMS, MWD, and PIP. BChOA ultimately proved to be more energy-efficient across the board. On average, it used 7.73% less energy than GA, 4.50% less than PSO, and 1.71% less than ACO. We also examined where each of these methods excelled and where they fell short, all within the context of task mapping for NoC-based heterogeneous MPSoC systems.

As one of the most significant parts in the development of the next generation infrared detection system, the infrared signal processing system requires the ability of real-time processing and high speed data transmission. A newly developed real-time signal processing system for infrared detecting based on the heterogeneous multiprocessor system on chip (MPSoC) is proposed in this paper. The device follows the architecture of Xilinx Zynq platform, integrating a feature rich dual-core ARM and Xilinx FPGA in a single chip, built on the 28nm high-k metal gate process technology. According to our design, the FPGA fabric portion retains all the programmable flexibility to drive the infrared detector and acquire data from ADC, with registers parallel operations to implement hardware acceleration. Furthermore, the FPGA fabric is connected to the ARM centered processor unit through multiple high performance interfaces, confirming high bandwidth communication and high speed data transmission between the two portions. Finally, the dual core ARM takes charge of the infrared signal processing system in general. One of the CPUs controls separate hardware modules and maintains the GUI for user interaction. The other responds to the dedicated system commands and external interrupts to update system parameters simultaneously. The integration of ARM and FPGA provides levels of performance that two-chip solutions cannot match due to their limited I/O bandwidth, loose coupling and power budgets. Experiments show that the architecture of heterogeneous MPSoC enhances the efficiency of memory controller and increases the speed of data transmission, approaching the theoretical value of the interfaces bandwidth.

The design of a Multiprocessor System-on-Chip (MPSoC) is a complex task, including steps as application development, platform configuration, code generation, task mapping onto the platform and debugging. An integrated environment covering most of these steps is a gap in the literature. The present work first details an MPSoC architecture, which supports the execution of distributed applications, including an operating system enabling multitask execution at each processing element. The MPSoC is heterogeneous, due to the support to different processor architectures. Then, a framework able to cover the design steps previously mentioned is presented. The framework enables the design space exploration for applications to be executed in the MPSoC, varying for example the number and type of processors, the memory size, the task mapping. Results demonstrate the correct operation for different MPSoC configurations, generated from the proposed framework. Such open-source framework enables the research community to investigate new subjects related to MPSoC and Network on Chip (NoC) design, as well as evaluate distributed applications in a multiprocessor environment.

Multiprocessor Systems-on-Chip (MPSoCs) are a promising solution to fulfill the requirements of high performance computing applications, such as image processing or bioinformatics. Many different MPSoC architectures are introduced by industry and academics, such as Intel's Single Cloud Computer (SCC) or IBM's Cell. To achieve a high efficiency on such MPSoCs a high computing performance in the processing elements (PE) is not the only parameter. The bandwidth of the memory and especially the on-chip communication infrastructure are extremely important to achieve the requirements of the applications. Furthermore, for embedded System-on-Chip solutions, flexibility is extremely important for providing a good tradeoff between performance and power consumption. Especially, for general purpose MPSoCs, designed for a wide range of applications with different communication demands, this flexibility is essential for a good energy efficiency. A simple bus or Network-on-Chip (NoC) with fixed bandwidth and communication paradigm is not sufficient in this varying application scenario and its design space. In this paper novel features for the heterogeneous and runtime adaptive Star-Wheels Network-on-Chip are presented. This Network-on-Chip is used within a runtime adaptive MPSoC, which enables to tailor processors and accelerators to the requirements of the applications. For optimizing the Star-Wheels Network-on-Chip and its communication protocol at runtime to the application requirement the following novel features have been added: the combination of the circuit- and the packet-switched communication paradigm and an algorithm-based placement of the processing elements within the NoC. The integration of the novel algorithm into the design methodology and the exploitation of the novel features within the special purpose runtime operating system of a runtime adaptive MPSoC are also introduced.

The efficient design of mapping solutions for heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) is usually a challenging task in system-level design, in particular when the architecture integrates hardware cores. This paper proposes a SystemC simulation framework for fulfilling this task featuring (i) an automated flow for the generation of SystemC timing models for the hardware cores starting from the application source code, and, in a second step, (ii) the possibility to simulate different mapping solutions simply by changing an XML descriptor and without any interaction of the designer. The proposed framework has been then applied to a case study considering an image processing application to present the possibility to integrate it as an evaluator in design space exploration environments.

Embedded System plays a vital role in consumer Industry. Complex applications need systems which contains multiple heterogeneous processors, running in parallel to speed up the system. Also due to area constraints, the processors are evolved in a single System on Chip called Multiprocessor System on Chip (MPSoC). The system should be reusable and debuggable, hence the designers designed and developed Reconfigurable MPSoCs rather than Application Specific Integrated Circuits (ASIC) in Field Programmable Gate Arrays (FPGA). Multiprocessor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However the growth of number of processing elements in one chip, task decomposition and scheduling become major bottlenecks of MPSoC architecture. To execute the applications, the application software is splitted as tasks and mapped to the different available processors and scheduled the tasks as when to execute in the available processors when the resources are ready. Selection of most suitable candidates for execution in a particular processor is very much important. Hardware related tasks are executed in different hardware accelerators and software tasks in processors. The area occupied by the schedulers in memory is more in internal memory. For scheduling these tasks, a programmable hardware is developed as hardware scheduler in the reconfigurable MPSoC using NIOS II processor. The algorithm for optimized scheduling in the target architecture is proposed. The literature survey is made with the hardware scheduler and new target MPSoC architecture. Quartus II version 12.1 and SOPC Builder are used to configure the NIOS II processer. Nios II EDS software tool has been used to build the application code.

Programming Multiprocessor Systems-on-Chips (MPSoCs) with hundreds of heterogeneous Processing Elements (PEs), complex memory architectures, and Networks-on-Chips (NoCs) remains a challenge for embedded system designers. Dataflow Models of Computation (MoCs) are increasingly used for developing parallel applications as their high-level of abstraction eases the automation of mapping, task scheduling and memory allocation onto MPSoCs. This paper introduces a technique for deploying hierarchical dataflow graphs efficiently onto MPSoC. The proposed technique exploits different granularity of dataflow parallelism to generate both NoC-based communications and nested OpenMP loops. Deployment of an image processing application on a many-core MPSoC results in speedups of up to 58.7 compared to the sequential execution.

Multiprocessor system-on-chip (MPSoC) platforms have been emerging as the main solution to cope with processor frequency ceiling and power density issues while still improving performances. Then, network-on-chip (NoC) has been adopted to provide the increasing number of processors with the required communication bandwidth as well as with the necessary flexibility. Video processing and streaming applications are adopting dynamic dataflow model of computation as the need for high performance parallel computing is growing. Dataflow applications executed on modern MPSoC-based architectures are becoming increasingly dynamic and more data-dependent. Different tasks execute concurrently with significant modifications in their workloads and resource demanding over time depending on the input data. Hence, adopting any static or offline dynamic scheduling for mapping tasks will not cope with the computation variations. This article introduces an original run-time mapping algorithm based on the Move Based (MB) method targeting a dedicated heterogeneous NoC-based MPSoC architecture to achieve workload balancing and optimized communication traffic. The performance of the proposed algorithm is verified by conducting cycle-accurate SystemC simulations of the adopted NoC implementing a real MPEG4-SP decoder. The obtained results reveal the effectiveness of our proposed algorithm. For various real-life videos, the proposed algorithm systematically succeeded to enhance significantly the performance.

Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption.

Multiprocessor systems on chips (MPSoCs) are envisioned as the future of embedded platforms such as game-engines, smart-phones and palmtop computers. One of the main challenge preventing the widespread diffusion of these systems is the efficient mapping of multitask multimedia applications on processing elements. Dynamic solutions based on task migration has been recently explored to perform run-time reallocation of task to maximize performance and optimize energy consumption. Even if task migration can provide high flexibility, its overhead must be carefully evaluated when applied to soft real-time applications. In fact, these applications impose deadlines that may be missed during the migration process. In this paper we first present a middleware infrastructure supporting dynamic task allocation for NUMA architectures. Then we perform an extensive characterization of its impact on multimedia soft real-time applications using a software FM Radio benchmark.

The progressive maturity of VLSI manufacturing technology is helping in integrating more and more processing elements and memory units on a single die to form a Multiprocessor System-On-Chip (MPSoC). Network-on-Chip (NoC) is adopted as communication backbone for most of these modern day multiprocessor systems. As complexity of these system scales, there has been a growing concern on the dependability of these processing and communication elements. In this paper, we propose a centralized hardware fault-tolerant network interface (NI) for NoCs based on spatial division multiplexing. Experiments show that the proposed design has better throughput than a non fault-tolerant design with only 18% area overhead. We also introduce an area optimized distributed fault-tolerant NI architecture which provides 50% more throughput than the centralized design for high fault rates.

Run-time task migration in a heterogeneous multiprocessor system-on-chip (MP-SoC) is a challenge that requires cooperation between the task and the operating system. In task migration, minimization of the overhead during normal task execution (i.e., when not migrating) and the minimization of the migration reaction time are important. We introduce a novel technique that reuses the processor's debug registers in order to minimize the overhead during normal execution. This paper explains our task migration proof-of-concept setup and compares it to the state-of-the art. By reusing existing hardware and software functionality our approach reduces the run time overhead.

Network-on-Chip (NoC)-based multiprocessor system-on-chips (MPSoCs) are becoming the de-facto computing platform for computationally intensive real-time applications in the embedded systems due to their high performance, exceptional quality-of-service (QoS) and energy efficiency over superscalar uniprocessor architectures. Energy saving is important in the embedded system because it reduces the operating cost while prolongs lifetime and improves the reliability of the system. In this paper, contention-aware energy efficient static mapping using NoC-based heterogeneous MPSoC for real-time tasks with an individual deadline and precedence constraints is investigated. Unlike other schemes task ordering, mapping, and voltage assignment are performed in an integrated manner to minimize the processing energy while explicitly reduce contention between the communications and communication energy. Furthermore, both dynamic voltage and frequency scaling and dynamic power management are used for energy consumption optimization. The developed contention-aware integrated task mapping and voltage assignment (CITM-VA) static energy management scheme performs tasks ordering using earliest latest finish time first (ELFTF) strategy that assigns priorities to the tasks having shorter latest finish time (LFT) over the tasks with longer LFT. It remaps every task to a processor and/or discrete voltage level that reduces processing energy consumption. Similarly, the communication energy is minimized by assigning discrete voltage levels to the NoC links. Further, total energy efficiency is achieved by putting the processor into a low-power state when feasible. Moreover, this approach resolves the contention between communications that traverse the same link by allocating links to communications with higher priority. The results obtained through extensive simulations of real-world benchmarks demonstrate that CITM-VA approach outperforms state-of-the-art technique and achieves an average ~30% total energy improvement. Additionally, it maintains high QoS and robustness for real-time applications.

Nowadays, the growing complexity in a wide variety of applications has led to the use of Multiprocessor Systems-on-Chip (MPSoCs). Networks-on-Chip (NoCs) have emerged as a scalable intra-chip communication technology for a high number of processing elements. However, the evolution of MPSoCs shows increasing communication requirements due to the growing number of PEs. This paper presents a novel Network-on-Chip microarchitecture that combines data transfers with data stream processing to exploit efficiently the transmission time. Data stream processing is enabled by a lightweight processing unit that is located within the transmission channels of the NoC. Thus, data can be processed by operations either in a processing element such as a MicroBlaze processor or inside the NoC while it is transferred. Operations executed by the NoC reduce the workload of the processing elements. In addition, the transmission time will be efficiently used. The novel microarchitecture is evaluated and compared to a state-of-the-art router on a Xilinx Zynq FPGA.