Processing and Reliability of New 3D-Wlcsp Package Technology

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.

Redundant cells are added to a memory chip to replace defective cells during IC fabrication to increase overall wafer yields. Compared to other repairing methods, only a small chip area is needed to design laser fuses, moreover, just a few redundant rows or columns can significantly enhance the yields of memory wafers. The laser fuses are hence the most commonly implemented method to increase yields in both DRAM and SRAM IDMs. In conventional memory packages, either TSOP II or FBGA, the memory chips are probed and repaired first, then packaged, burn-in, and final test. Therefore, there is no issue in covering the laser windows on a memory chip after laser repairs since the laser windows are all encapsulated by molding compound. In flip chip technologies or wafer-level packaging, memory ICs are packaging in wafer forms instead of individual dies. Moreover, memory wafers are normally probed and repaired before packaging, therefore, the laser windows are also encapsulated by underfill materials or by molding compound. However, if the conventional chip probing, burn-in, and laser repair can be done after flip chip bumping or wafer-level packaging, the testing steps can be simplified, the testing cost can be greatly reduced, and more wafer yield can be gained. This study primarily focuses on the laser repair after flip chip bumping to explore the feasibility of laser repair through BCB passivation on top of laser fuses and to develop new processes to protect laser fuses during flip chip bumping. Three different conditions are studied, original laser windows with PI passivation opened, laser windows with BCB coated on the top of PI passivation, and laser windows with BCB coating without PI passivation. The laser windows with PI opened, the laser fuses can easily be “burned” with 1.0 μJ of laser energy and the die can successfully be repaired since a fuse is sublimated by the laser beam with its vapor exploded and broken through the covered dielectrics. There are two different thicknesses of coated BCB in laser windows, one is laser windows with BCB coated on the top of PI passivation and the other is laser windows with BCB coating without PI passivation where the thicknesses are 10.69 μm and 7.32 μm, respectively. The results of laser repair are almost identical. Even with the laser repair energy up to 1.8 μJ, the fuse can not be “burned” and its vapor can not explode and break through the dielectrics and the BCB on top, all the more, its vapor will go sidewards and cause cracks along the interfaces of BCB and the dielectrics, in the worst case, causing shorts between the adjacent fuses. From the results of the laser repair, it can easily be concluded that the fuse vapor cannot easily break through the dielectrics with a thick BCB on top, therefore, no further study on the parameters of laser repair through BCB is necessary. The laser repair should be performed without any BCB passivation nor any bumping residual inside the laser windows. Then, how to protect laser fuses inside the laser windows during flip chip bumping processes becomes very crucial. The protection of laser fuses can be done by using appropriate UBM materials during flip chip bumping processes, then after solder ball reflow, the UBM was removed by etching. It has been proven that the dielectrics on top of laser fuses will not be damaged during flip chip bumping processes.

In the last few years, flip chip technology has been increasingly employed in a variety of applications in the microelectronics industry. Comparing to conventional wirebonding technology, flip chip provides lower profile, faster signal transfer, and higher I/O density. One of the key materials used in flip chip is the underfill encapsulant, which enhances the reliability of the flip chip device by more than an order of magnitude. Currently, underfilling is carried out at the package level, e.g., each chip has to be processed individually after solder reflow. The encapsulant has to be post-cured subsequently off-line. The slow underfilling process becomes a bottleneck in the high volume manufacturing of flip chip. A joint venture program, sponsored by the Advanced Technology Program (ATP), was formed to explore the next paradigm shift in flip chip packaging technology, namely, processing underfill at the wafer level. In this process, the underfill is deposited on the wafer prior to dicing. At the assembly stage, the singulated die is processed as in standard flip chip reflow operations. The main difference is that the pre-coated underfill with built-in flux will cure concurrently with the reflow of the solder, allowing both electrical and structural interconnection to be achieved simultaneously. Therefore, this wafer level underfill process offers much potential in terms of reduced production time and increased throughput. The process will be directly suitable for high volume production using the existing assembly infrastructure, lowering the cost of implementation. In this paper, the technical challenges and the solutions for both materials development and process verification in this program will be discussed.

Electroplating is by far the most promising process to fabricate fine pitch solder bumps in flip chip. However, rugged surface and poor coplanarity resulted from numerous variable plating parameters generally cause short circuit and broken circuit to affect packaging reliability. With the great demand for decreasing pitch size below 100 um, solder bumps' coplanarity would become more and more important as considering alignment in advanced three-dimensional packaging and WLP (Wafer Level Packaging). This paper aims to provide a creative solder bump fabrication process that is characterized by using a polishing mechanism to transform the plated solder bumps with huge height deviation into smooth and uniform ones. Predominately in mechanical polishing force enables it to polish much wider height deviation, typically affected by poor current distribution in tiny area plating. Equipped with a specific soft non-woven polishing pad and a self-designed substrate holder, the polisher features large MRR (Material Removal Rate), easy manipulation and high efficiency. The final experimental results indicate that the polishing rate in lead-free Sn-Cu solder bumps could reach as fast as 4~5 um/min, almost 50 times faster than CMP (Chemical Mechanical Polishing). The whole coplanarity of solder bumps at 80 um pitch size could be sharply decreased from 33plusmn2.5 um (7.5%) after plating to 28plusmn1 um (3%) after polishing and even 26plusmn0.5 um (1%) after re flow. Most importantly, each single die (6 mmtimes6 mm) after re flow could be controlled as accurately as within 0.5%. This proposed polishing mechanism could assist the plating-based solder bumps in precisely getting better coplanarity so as to enhance packaging reliability and yield.

The application of organic materials used in IC advanced packaging:A review

Emerging markets are always driving demand for higher performance, higher bandwidth, lower power consumption as well as increasing functionality in mobile applications. Packaging technology has become more challenging and complicated than ever before, driving advanced silicon (Si) nodes, finer bump pitch as well as finer line width and spacing (LW/LS) substrate manufacturing capabilities to satisfy the increasing requirements in the semiconductor industry. As increasing input/output (I/O) counts in a package are needed in mobile devices, packaging solutions are migrating from traditional wire bond packages to flip chip interconnect to meet these requirements. Flip chip chip scale package (fcCSP) is viewed as an attractive solution for complicated and highly integrated systems with multiple functions and heterogeneous mobile applications. Although emerging markets are driving advanced technologies in high performance mobile devices, assembly cost is still the major issue to be addressed. In addition, due to the fast growth in emerging markets for mobile applications, advanced Si node technology development for mobile applications is moving to 10nm technology (and below) and pursuing the die size reduction, efficiency enhancement and lower power consumption now. For the sake of realizing the 10nm extremely low-k (ELK) performance in a flip chip package, this paper address the technology of Mediatek innovation package (MIP) design by using copper (Cu) pillar bond-on-lead (BOL) with embedded trace substrate (ETS) to achieve low cost, finer bump pitch as finer LW/LS requirements. The 10nm chip-package interaction (CPI) study in a 15×15mm fcCSP with finer Cu pillar bump pitch of 60μm and a 2-layer ETS with finer LW/LS design is illustrated. The utilizations of 60μm bump pitch with escaped trace and mass reflow (MR), thermo-compression bonding (TCB), TCB with non-conductive paste (TCNCP), and laser assist bonding (LAB) flip chip attach process are estimated. The quick temperature cycling (QTC) test with temperature range of -40°C to 60°C is performed to realize the ELK performance in this 10nm flip chip package. Moreover, the comparison of different under bump metallization (UBM) sizes, existence of polyimide (PI) layer and reflow profiles has been also studied. With the evaluated results, not only the significant factors that impact ELK performance can be obtained, but the optimized reflow profile can also be established to enhance the yield in flip chip attach processes. It is believed that the illustrated robust flip chip attach processes examined in this paper can guarantee 10nm fine bump pitch flip chip assembly yield with less ELK damage risk in the future.

There are multiple technologies to choose from when building a microelectronics package. First-level packaging refers to the process of creating electrical connections between an integrated circuit and a printed circuit board. The package does not only route electrical connections, but also provides protection from the environment, mechanical stability, and more. Although the cost of silicon tends to represent the majority of the total cost of a package, the cost of the packaging process itself is not negligible. Even cost savings of one cent can have a meaningful impact. This paper will present a cost breakdown and cost driver analysis for three packaging technologies: wire bond, flip chip, and wafer-level packaging. Activity based cost modeling will be used to analyze all aspects of cost, including capital, material, labor, and yield. Process flows for all three technologies will be included. The goal of this analysis is to highlight design features that impact cost for wire bond, flip chip, and wafer-level packages.

A variety of flip chip technologies are available today which differ in bumping material, substrate type, pad metallization and joining method. They are found in packages as well as on multichip modules and directly flip chip bonded on the board. Components including flip chip like ball grid arrays and chip size packages are introduced. Flip chip is the most favored assembly technology for high frequency applications due to the small parasitic of the short bump interconnect. High performance packages for optoelectronic devices using self-alignment during a fluxless reflow soldering are shown as well as the integration of MMICs. High density multichip modules have been fabricated for large pixel detectors of a nuclear detector with eight Chips and more than 46000 I/Os with an acceptable yield. Flip chip technology is a very flexible assembly method for different applications. Variations of the bump structure can be used for MEMS packaging as well and it was demonstrated by the assembly of a thin membrane to form an absolute pressure sensor with a vacuum enclosure. For different packaging requirements the appropriate technology should be chosen very carefully. An overview will be given for different bumping and flip chip joining methods suitable for high volume production as well as for prototyping. Wafer bumping methods will focus on electroless deposition of nickel/gold as well as on electroplating of gold, SnPb and AuSn solders. For rapid prototyping single chip bumping methods are described. Examples of different joining methods - soldering, adhesive bonding and thermocompression bonding - will be shown.

System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever smaller products is continuously pushing development of new materials, components and assembly technologies. An optimization study of a SiP design based on a functional product is discussed in this presentation to address the following: 1. Design optimization to reduce component spacing with varied assembly challenges 2. Substrate stack-up optimization for z-height reduction with coreless substrate technologies 3. Flip chip (FC) bump pad optimization for ball bumped or copper-pillar bumped CMOS silicon's 4. Cost reduction potential to replace SOP with paste printing using u-stencil for flip chip applications 5. Assessment of different MUF and fluxing underfill (FU) materials To accomplish these objectives, two types of bumped silicon wafers/dice, three different substrates and four different materials were implemented in this DOE. Short-looped wafers of an actual live device were bumped with CuP pillar as well as with SnAg ball bumping technologies. All three substrate designs are coreless, as compared with the original POR conventional design. One substrate was designed with the plan-of-record (POR) component spacing on a 6-layer stack-up that results in ∼ 290 um overall z-height; X-Y-Z size reductions were achieved on the alternative 4-layer design that has reduced component spacing as well as a reduced overall z-height of ∼ 190 um; furthermore, embedded trace substrate (ETS) was used as the top layer for the 4-layer designs to ensure improved routing capabilities. Subtle differentiation between these two 4-layer designs is in the die shadow area on the top ETS layer: while one design uses solder mask defined pads (SMD) the other uses the ETS dielectric materials to define the flip chip bonding pads without solder mask (NSMD). The latter design facilitates the MUF flows for ultralow stand-off flip chip solder joints and make it a likely “universal” pad design for both CuP and SnAg flip chip bump attach. Four different MUF materials along with one FU materials were used for DOE assembly: the first MUF is the POR material currently used in HVM production with nominal filler sizes; 2nd MUF is for low warpage applications (especially for thin, coreless substrate); 3rd MUF has a smaller filler size that is optimized for small stand-off flip chip bumps and the last MUF has a much improved thermal conductivity and is assessed here for its fit-for-use in other high thermal density applications. FU used is an underfill material with build-in flux and is opportunistically included here to assess its fit for use for our future products. Overall DOE plans shall be described, preliminary results as well as the screening test plan will be presented in some detail and implication of these interacting factors in improving a SiP design to achieve small form end product will be discussed.

Wafer level packaging technology, as an advanced packaging technology with high maturity and wide application, has been widely used in portable products such as mobile communication. This paper mainly introduces two kinds of wafer level chip scale package forms, fan in and fan out, introduces the whole process of fan-out wafer level package and finally looks into the future development trend of wafer level chip scale package technology.

A low-cost, highly reliable UFI (UBM-free integration) wafer level chip scale packaging (WLCSP) for high performance, large die (>100 mm2) with fine solder ball pitch (350 µm) and high I/O (>800) has been developed. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5x5 mm2 with ball pitch smaller than 350 µm. In this paper, we present the novel WLCSP designed with a stress-mitigation structure which can significantly enhance the reliability of the package and enables die size extension. By controlling the maximum strain location and optimizing the materials using the stress-mitigation structure, the chip warpage and the stress between Si and PCB can be effectively reduced to enhance both component and board-level reliabilities of the package. The UFI WLCSP passed all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution (t63), respectively. As a result, highly reliable packages with various die sizes, including 5.2x5.2, 7.2x7.2 and 10.3x10.3 mm2 and with both 400 and 350 µm ball pitches have been developed. The RDL within the package of UFI WLCSP can be utilized to form inductor structure which exhibits quality-factor nearly 50% higher than that of an on-chip inductor. Besides, in WLCSP process, die sawing typically causes delamination and cracking of packages which results in process failure in the WLCSP. The UFI unique structure consists of sidewall protection which is capable of preventing chipping and therefore effectively improves the process controls and the reliability margins. In addition, to fulfill the requirement of high I/O products and to enhance the design flexibility, we embedded multiple RDL in UFI WLCSP with die size of 10.3x10.3 mm2 and ball pitch of 350 µm, which provides a fan-in package solution with I/O >800. The large die UFI WLCSP has passed the component-level reliability tests of TCB1000, uHAST96 and HTS1000, and board-level reliability tests of TCG500 and drop tests.

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

Reliability of flip chip CSP (Chip Scale Package) was investigated. The underfill resin for CSP has high saturation content of moisture absorption, compared to a conventional mold resin. The IR reflow test showed no delamination at the underfill interfaces and no package cracking in a flip chip CSP with a ceramic substrate and voidless underfill under the JEDEC LEVEL 1 and 2 conditions. However, it was found out that delamination and package cracking occurred in the IR reflow test under the JEDEC LEVEL 1 when the flip chip CSP has voids in the underfill. The underfill reliability results by IR reflow test confirmed superior reliability of the flip chip CSP with a ceramic substrate and void controlled underfill.

Packaging technologies such as fan out wafer level packaging (FOWLP) and embedded chip in substrate technologies have gained a lot of attention recently from OEMs, OSATS, technology developers, and technology integrators in the integrated circuit (IC) industry as schemes for continuing wafer level chip scale package (WLCSP). Both technologies are focused on incorporating ICs into their packaging platform and on taking advantage of current process recipes and infrastructure as much as possible. However, by virtue of the new process steps and technologies required to get to 3-D packaged materials, such as through silicon vias (TSVs), wafer thinning and handling processes and requirements for alternative dielectric materials, many opportunities have arisen. Expectations are that many devices that follow a flip chip ball grid array (FCBGA) flow or WLCSP will adopt an embedded technology strategy for future generations. FOWLP has several advantages, over FCBGA and WLCSP including potential for system in package (SIP) configurations and 3-D integration, the ability to overcome pad limitation issues, and shorter interconnections and so higher electrical performance. However, to gain these advantages, requirements for processing will change due to the significant demands imposed on the materials used as permanent dielectric layers and the photoresists used in the fabrication processes. Cleaning chemistry must be designed to remove challenging films such as photoresists and residues created during other process steps; yet preserve the exposed metals such as the bond pads and Cu redistribution lines, as well as the permanent dielectrics. Device reliability and performance is heavily dependent on the proper working of all these components. The focus of this paper is to identify a manufacturable and reliable process and process window for removal of positive photoresists and residues in formation of under bump metallization (UBM) and contact pads in wafer level packaging (WLP). Our objective is to discuss a proven process that has been successfully implemented into a manufacturing environment. It has improved robustness and reliability over past-used solutions due to decreased sensitivity to moisture contamination, a significant cause of defects in many device applications.