Program Assemblers

The traditional form of recording machine code is assembly language. Its commands correspond directly to individual machine commands or sequences of commands. The syntax of an assembly language program is determined mainly by the instruction system of the specific processor and the directive system of the specific translator. For some platforms, there may be several kinds of assembly language syntax that are not compatible with each other. For example, the most popular assembly language syntaxes for Intel-compatible processors are Intel syntax and AT&T syntax. However, all existing types of assembly language syntax are primarily focused on easy readability by the computer, not the programmer. The system of symbolic macro commands of the processor presented in the article is a more clear form of representation of machine code, which promotes productivity when the programmer works with it, and also minimization of errors.

The most convenient way of writing and running assembly language programs on the ZX81 computer is to use an assembler program to carry out the translation from assembly language to machine code. A suitable assembler program is ZXAS. If an assembler is not available, programs can be translated manually; this process is known as hand assembly and is described in detail in Appendix B. After the program has been translated into machine code it can be run by the computer and any errors in the program can be found and corrected. This is a more difficult process with assembly language programs than it is with BASIC programs. The process can be made easier by the use of a program which helps you to examine what is happening inside the computer while your program is running. A program of this type is called a debugger and for the ZX81 the program ZXDB performs this invaluable task.

Packet filters play an essential role for network traffic/security management in today's Internet. To make software-based packet filters so fast that could work even in suffering from DOS attacks, the authors are challenging to effectively combine both the higher-level optimization relating to algorithmic structure adapted to the input packet sequence and the lower-level one relating to acceleration techniques in compiler study. In this paper, we focus on the lower-level (machine code) optimization using software pipelining, and report preliminary experimental results indicating that our approach has great potential to accelerate packet filter performance. Our code optimization achieves more than ten times higher performance compared with a conventional interpreter-based packet filter for each of seven typical fragments of packet filter rules

This study examines vectorized programming for finite impulse response image filtering. Finite impulse response image filtering occupies a fundamental place in image processing, and has several approximated acceleration algorithms. However, no sophisticated method of acceleration exists for parameter adaptive filters or any other complex filter. For this case, simple subsampling with code optimization is a unique solution. Under the current Moore’s law, increases in central processing unit frequency have stopped. Moreover, the usage of more and more transistors is becoming insuperably complex due to power and thermal constraints. Most central processing units have multi-core architectures, complicated cache memories, and short vector processing units. This change has complicated vectorized programming. Therefore, we first organize vectorization patterns of vectorized programming to highlight the computing performance of central processing units by revisiting the general finite impulse response filtering. Furthermore, we propose a new vectorization pattern of vectorized programming and term it as loop vectorization. Moreover, these vectorization patterns mesh well with the acceleration method of subsampling of kernels for general finite impulse response filters. Experimental results reveal that the vectorization patterns are appropriate for general finite impulse response filtering. A new vectorization pattern with kernel subsampling is found to be effective for various filters. These include Gaussian range filtering, bilateral filtering, adaptive Gaussian filtering, randomly-kernel-subsampled Gaussian range filtering, randomly-kernel-subsampled bilateral filtering, and randomly-kernel-subsampled adaptive Gaussian filtering.

Incorporating user-oriented features usually found only in much larger computers, the first models of the Eclipse line, the $100 and $200, use a high speed micro-programmed central processor, and can run with either; core or semiconductor memories, or both. The core and semiconductor memories are available with an error detection and correction feature that can find and correct; single bit errors caused by the computer. The semiconductor memories use a high-speed cache to increase memory speed. The Eclipse $100, the smaller of the two computers, will be used by oems or by end users who need a smaller system to meet their requirements. The Eclipse $100 is 5-1/4 inches high, and holds six standard Data General printed circuit boards. It costs $9200, with 16k bytes of core memory, and $10,700 with 16k bytes of semiconductor memory. Eclipse $100 deliveries will begin in December. The Eclipse $200, a system-oriented computer that can hold 16 printed circuit boards, will be used by system builders or end users who will build large scale computing systems around it. The Eclipse $200 is 10-1/2 inches high, and costs $16,300 with 32k bytes of core memory, and $19,300 with 32k bytes of semiconductor memory. Deliveries of the Eclipse $200 will begin in February. The instruction set of both Eclipse computers is microprogrammed in the central processor. There are over 40 new instruction in the Eclipse computers. Programs written on Nova computers will run on either the Eclipse $100 or $200. The central processor includes a Writeable Control Store making up to 256, 56-bit words available to write specialized micro-programmed instructions. The instruction set is enhanced to help programmers writing in assembly language or high-level language programs. Hardware memory stacks, supported by comprehensive instructions, make programming more efficient, while block, word, byte and bit manipulation instructions improve system performance. Instructions are both single word and double word instructions.

3 - The Program Assembler and Debugger

A method has been developed for evaluating central processing unit (CPU) coverage by automatically injecting faults into actual CPU hardware while it is executing relevant test software. A special hardware test fixture is used which contains the CPU under evaluation, program and data memory, and a terminal interface. The test fixture is connected to a microcomputer controller and an in-circuit read only memory (ROM) emulator. The faults injected are stuck-at-1, stuck-at-0, and open on the appropriate integrated circuit pins, plus the altered state of every microprogram memory bit. The effect of each fault is determined by observing the status of the monitor. Data reduction is performed after each run on a separate host computer, and summary results are tabulated. N digital avionics systems the central processing unit (CPU) is obviously the dominant functional element, upon which many other elements are dependent in order to perform correctly related interface and control tasks. Normally, there are arrays of system monitors, in both hardware and software, which have an inherently overlapping capability to detect CPU malfunctions. The combined effectiveness of these monitors determines the total CPU fault coverage. However, since many of these monitors are themselves dependent upon CPU operation, there is a critical topdown relationship between the monitors which must be considered. In particular, a software monitor is of little subsequent value in the presence of a CPU fault unless one of the two following conditions is present. 1) It is actually executed, and it produces the planned fault detection results, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. 2) It causes fault detection elsewhere when it is not executed, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. In simplest terms, software monitors depend upon a rational CPU; that is, a CPU which is at least able to follow the normal program flow without making addressing or branching errors. If this is not the case, then how can one guarantee that the software monitor is executed? If it is possible to detect the fault of concern without executing the software monitor, then why is the monitor present? The point is that it is critically necessary to have a CPU monitoring scheme which establishes the minimum CPU fault coverage that is required to support all other monitoring activity. Such a monitoring scheme must straddle the hardware-software boundary so that external communication is absolutely guaranteed. In the simple terms introduced in the preceding, such a monitor must be able to detect all faults resulting in irrational CPU operation. In most modern digital avionic systems, the monitor which does these things is the so-called watchdog monitor (WDM) (or alternately the heartbeat or deadman timer monitor). The WDM usually operates in relation to the timer

We have implemented the Martini force field within Lawrence Livermore National Laboratory's molecular dynamics program, ddcMD. The program is extended to a heterogeneous programming model so that it can exploit graphics processing unit (GPU) accelerators. In addition to the Martini force field being ported to the GPU, the entire integration step, including thermostat, barostat, and constraint solver, is ported as well, which speeds up the simulations to 278-fold using one GPU vs one central processing unit (CPU) core. A benchmark study is performed with several test cases, comparing ddcMD and GROMACS Martini simulations. The average performance of ddcMD for a protein-lipid simulation system of 136k particles achieves 1.04 µs/day on one NVIDIA V100 GPU and aggregates 6.19 µs/day on one Summit node with six GPUs. The GPU implementation in ddcMD offloads all computations to the GPU and only requires one CPU core per simulation to manage the inputs and outputs, freeing up remaining CPU resources on the compute node for alternative tasks often required in complex simulation campaigns. The ddcMD code has been made open source and is available on GitHub at https://github.com/LLNL/ddcMD.

A new algorithm for massively parallel calculations of electron correlation energy of large molecules based on the resolution of identity second-order Møller-Plesset perturbation (RI-MP2) technique is developed and implemented into the quantum chemistry software NTChem. In this algorithm, a Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) hybrid parallel programming model is applied to attain efficient parallel performance on massively parallel supercomputers. An in-core storage scheme of intermediate data of three-center electron repulsion integrals utilizing the distributed memory is developed to eliminate input/output (I/O) overhead. The parallel performance of the algorithm is tested on massively parallel supercomputers such as the K computer (using up to 45 992 central processing unit (CPU) cores) and a commodity Intel Xeon cluster (using up to 8192 CPU cores). The parallel RI-MP2/cc-pVTZ calculation of two-layer nanographene sheets (C150H30)2 (number of atomic orbitals is 9640) is performed using 8991 node and 71 288 CPU cores of the K computer.

More efficient and compact thermal management techniques are critical for the development of Central Processing Units (CPU) embedded in complex and powerful modern computer systems. Introducing a technological alternative to conventional fan-cooled systems, this paper presents an experimental investigation of a double-action CPU cooler based on the pulsed (or synthetic) jet principle. The study develops a prototype of this new CPU cooler and tests it for a range of operating conditions to ascertain its cooling capabilities. The performance of this device is compared with a conventional fan CPU heat sink design for evaluating the relative thermal advantages of the new configuration. It is observed that the pulsed-jet CPU cooler achieves about 1.5 times more heat removal rate than a comparable fan CPU cooler. Whilst thermal optimisation is feasible, it is recognised that this pulsed jet arrangement has unique surface cooling ability without additional fluid circuits, making it particularly desirable for high-capacity electronic cooling applications.

In the world of supercomputers, the goal is higher and higher performance. To obtain the highest performance on a particular computational kernel, it is usually necessary to write assembly language. Compiler technology has not matured to the point of being able to take advantage many of the features of the i860 automatically. To approach the peak performance of the chip, it is currently necessary to use custom assembly language code. It is important to know which combinations of assembly instructions offer the highest performance, and which combinations cannot run at full speed. This paper assumes that you are already acquainted with the basics of the i860 microprocessor assembly language, and concentrates on describing how to enhance the performance of your code using 860 assembly language.

Sixteen Ss were asked to produce a random sequence of binary and ternary numbers in a counterbalanced within-S design. For each S and each condition, relative redundancy up to the fifth order was determined. Relative redundancy increased as a function of order of redundancy estimate significantly faster in the ternary-digit condition. It was concluded that it is more difficult to randomize items containing greater amounts of information.

A closed processor-sharing queueing model that corresponds to M terminals in series with a central processing unit (CPU) is considered under heavy usage conditions. The effects of switching times between the CPU and the individual jobs are included by assuming that the effective service rate that the CPU provides is a decreasing function of the instantaneous number of jobs being processed. Using perturbation methods, asymptotic expansions are constructed for the first two moments of a customer's response (sojourn) time, conditioned on that customer's total required service from the CPU. The asymptotic limit assumes that the number of terminals M is large $( M \gg 1 )$, that the rate at which the CPU provides service is fast $( O( M ) )$, and that the duration of a typical switching time is small compared to the time the CPU actually spends servicing the individual jobs. Extensive numerical comparisons show the quality of our asymptotic approximations.

This paper introduces the newly developed Infini- Band (IB) Management Queue capability, used by the Host Channel Adapter (HCA) to manage network task data flow dependancies, and progress the communications associated with such flows. These tasks include sends, receives, and the newly supported wait task, and are scheduled by the HCA based on a data dependency description provided by the user. This functionality is supported by the ConnectX-2 HCA, and provides the means for delegating collective communication management and progress to the HCA, also known as collective communication offload. This provides a means for overlapping collective communications managed by the HCA and computation on the Central Processing Unit (CPU), thus making it possible to reduce the impact of system noise on parallel applications using collective operations. This paper further describes how this new capability can be used to implement scalable Message Passing Interface (MPI) collective operations, describing the high level details of how this new capability is used to implement the MPI Barrier collective operation, focusing on the latency sensitive performance aspects of this new capability. This paper concludes with small scale bench- mark experiments comparing implementations of the barrier collective operation, using the new network offload capabilities, with established point-to-point based implementations of these same algorithms, which manage the data flow using the central processing unit. These early results demonstrate the promise this new capability provides to improve the scalability of high- performance applications using collective communications. The latency of the HCA based implementation of the barrier is similar to that of the best performing point-to-point based implementation managed by the central processing unit, starting to outperform these as the number of processes involved in the collective operation increases.

Convolution filtering is one of the most important algorithms in image processing. It is data-intensive, especially when dealing with high-definition images. Most previous studies on accelerating convolution computation in parallel focus on the use of graphics processing units (GPUs), whereas the central processing units (CPUs) always play the role of host to manage the data buffer and control flow. However, recent CPU architectures have seen significant modifications to parallel data computing capabilities, and the trend of integrating the CPU and GPU on a single chip is on a rise. We propose an approach to accelerate convolution filtering on the heterogeneous architecture of integrated CPU–GPU. We exploit the parallel processing power of vector instructions on a CPU and make it collaboratively function with the on-chip GPU. Two task assignment methods, static and dynamic task partitioning, are proposed for CPU–GPU collaboration. We evaluate our approach with images and filters of different sizes. The experimental results demonstrate that we can achieve 146 GFLOP/s at best using a quad-core CPU and the performance is 2.5 to 4.8 times faster than that of the single-GPU version of the OpenCV library. We also obtain 90 times speedup over the single-threaded CPU version. The results demonstrate that the proposed algorithm is efficient.