Prototype Implementation of Two Efficient Low-Complexity Digital Predistortion Algorithms

With the high interest in digital modulation techniques which are very sensitive to the PA nonlinearity, modern wireless communication systems require the usage of linearization techniques to improve the linear behavior of the RF power amplifier. The powerful and cheap digital processing technology makes the digital predistortion (DPD) a competitive candidate for the linearization of the PA. This thesis introduces the basic principle of DPD, its implementation on FPGA and the adaptive DPD system. The linearization of 4 PAs with DPD technique has been introduced: for the hybrid class AB PA operating at 2.6 GHz with a WiMAX testing signal, 33.7 dBm average power, 29.6 % drain efficiency, 13 dB ACPR and 9 dB NMSE improvement have been obtained; for the hybrid Doherty PA operating at 3.4 GHz with an I/Q testing signal, 35.0 dBm average power, 36.8 % drain efficiency, 12 dB ACPR and 13 dB NMSE improvement have been obtained; for the MMIC class AB PA operating at 7 GHz with an I/Q testing signal, 29.4 dBm average power, 25.7 % drain efficiency, 12 dB ACPR and 12 dB NMSE improvement have been obtained; for the two-stage PA operating at 24 GHz with an I/Q testing signal, 23.5 dBm average power, more than 14.0 % drain efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The DPD algorithm has been implemented on FPGA with two methods based on LUT and a direct structure with only adders and multipliers. The block RAM on the FPGA board is chosen as the table in the LUT methods. The linearization performance for these three methods is similar. The test PA is the hybrid Doherty PA mentioned above and the test signal is the I/Q signal with 7.4 dB PAPR. 35.1 dBm average power, 36.8 % efficiency, 11 dB ACPR and 11 dB NMSE improvement have been obtained. The cost of logic resources for the direct structure method is the largest with 1,172 flip-flops, while the number of flip-flops for the two LUT methods are 263 and 583, respectively. A new adaptive algorithm has been proposed in this thesis for the adaptive DPD system. This new algorithm improves the performance in extracting the model parameters in complex number domain. With the experimental data from a combined class AB PA, the final accuracy of the model extracted by the new algorithm has been improved from -20 dB to about -40 dB and the converge speed is faster

In this paper an implementation of the Inverse Numerical Laplace Transform (INLT) on a Field Programmable Gate Array (FPGA) is presented. A brief description of INLT algorithms based on FFT are made and its MATLAB implementation is performed in order to have a comparison basis with FPGA results. A fixed point representation is used and it is optimized using fi MATLAB object. INLT is basically composed by three stages: Windowing, FFT and exponential function multiplications, the last stage is considered the critical one because it can result in severely large errors, specially, when several samples are required. Errors can be reduced by increasing the number of bits, however this increment makes the required FPGA area greater. Windowing and FFT can be implemented with high accuracy on FPGA with CORDIC and Cooley Tukey algorithms respectively, making the implementation flexible. The implementation was made with Verilog description hardware language using Xilinx technology and Virtex 6 FPGA.

A robust and low sampling rate digital predistortion (DPD) algorithm for broadband power amplifiers (PAs) is proposed in this paper. To alleviate the burden on the sampling rate, an approximated model extracted by bandlimited signals is employed to approach the broadband behavior. Due to the assistance of the low pass filter (LPF) in the feedback loop and the adaptive basis function scheme, the sampling rate can be reduced drastically and the algorithm is more robust. Experimental results show that more than 21 dB adjacent channel power ratio (ACPR) improvement is achieved for 60MHz 3-carrier LTE signal application only with 92.16Msps sampling rate, and the cavity RF filter in the feedback loop is not necessary any more.

In this study, Field Programmable Gate Array (FPGA) implementation of Conic Section Function Neural Network (CSFNN) for a classification problem focused on iris plant is presented. This work demonstrates for the first time to our knowledge, the feed-forward computation of CSFNN implementation on FPGA. Using l6-bit floating point arithmetic and the look-up tables (LUTs) for the sigmoid function and the square root function, 83% and 72% of slices and LUTs on Spartan 3-E XC3S1600E are used for the realization of CSFNN with five neurons. The classification results obtained from the FPGA implementation and software simulation show that the accuracy error between two platforms is only 0.1%.

This paper deals with Field Programmable Gate Array (FPGA) implementation design of a Predistorter real-time processing. The corresponding Baseband Digital Predistortion (DPD) is based on Memory Polynomial (MP) modelling of a UHF 8 MHz LDMOS Power Amplifier (PA). The PA MP model coefficients are estimated based on Least Square Estimation (LSE) algorithm. The proposed DPD design is using Look Up Table (LUT) for the Predistorter unit and the Indirect Learning Architecture (ILA) approach for estimating the coefficients of the predistorter. Implementation test results for the UHF LDMOS PA with DVB-T modulated signals showed good linearization performances with the adjacent channel power ratio (ACPR) reaching −46 dB.

This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

In this paper we describe a single-node, double precision Field Programmable Gate Array (FPGA) implementation of the Conjugate Gradient algorithm in the context of Lattice Quantum Chromodynamics. As a benchmark of our proposal we invert numerically the Dirac–Wilson operator on a 4-dimensional grid on three Xilinx hardware solutions: Zynq Ultrascale+ evaluation board, the Alveo U250 accelerator and the largest device available on the market, the VU13P device. In our implementation we separate software/hardware parts in such a way that the entire multiplication by the Dirac operator is performed in hardware, and the rest of the algorithm runs on the host. We find out that the FPGA implementation can offer a performance comparable with that obtained using current CPU or Intel’s many core Xeon Phi accelerators. A possible multiple node FPGA-based system is discussed and we argue that power-efficient High Performance Computing (HPC) systems can be implemented using FPGA devices only.

This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

The design and measurements of a fabricated novel digitally programmable wideband power amplifier (PA) are presented. The PA is made suitable for use in all communication standards, including GSM, 3G, LTE and Femto-cells, offering a bandwidth of several octaves covering presently 300 MHz to 3.5 GHz. It meets power, efficiency and linearity specifications. The amplifier showed excellent performances. The uniquely linear and high power SONY GaAs J-PHEMT process along with novel output-stage multiple cascode topology structure are discussed. This enabled a distinctive larger output impedance and power and low voltage operation. The output stage offered 15–20 dB of gain without a driver. The circuit requires only little output or input matching for gain or impedance, depending on the application. In order to obtain higher gain and optimal application specific performance, a driver stage was added on the same die. A digitally programmable tuning chip was incorporated to the solution to optimize the performance for large bandwidths exceeding 40%. For smaller bandwidths no digital tuning was required. Digital pre-distortion algorithm was tested for better linearization. To the best knowledge of the authors, this is the first comprehensive plug-and-play solution for multi-band and multi-mode handset transmitters with the single chip one PA.

The drives of power amplifiers of magnetic levitation servo spindle applied to micro EDM (Electron discharge machining) based on FPGA (Field programmable gate array) are developed. The drive module that produces the PWM (Pulse width modulation) waves that conform to the requirements of spindle power amplifiers involving three-level half bridge switch power amplifier, three-level full bridge switch power amplifier and motor power amplifier, according to input of action values from magnetic levitation servo spindle controller DSP (Digital signal processor) is designed. Multi-PWM producing algorithm by single timer with multi comparing nodes is proposed. After being applied to control system of magnetic levitation servo spindle, the drives accomplish conversion from DSP action values to PWM waves. The PWMs that drive radial coil current power amplifier have phase difference of 180°. The PWMs that drive axial coil current power amplifier have dead zone time and their wave shapes are complementary. The PWMs that drive the motor power amplifier conform to requirements of power amplifier chip LMD18200. Using FPGA to realize the drive function of spindle power amplifier makes the drive design more flexible, resource distribution of DSP more optimized, the task of algorithms running more centralized, and the drives module gets simpler and more reliable because the phase shift circuit and dead zone circuit are cancelled but the function of phase shift and dead zone is reserved.

An adaptive, digital, baseband predistortion (PD) algorithm that compensates for the memoryless nonlinearities of radio-frequency (RF) power amplifiers (PAs) for wireless systems using non-constant-envelop modulation schemes is presented. Compared with the conventional, complex-gain predistorters based on lookup tables (LUTs), the proposed direct-learning, multilevel lookup table (ML-LUT) approach assisted by a hardware-efficient loop delay compensation scheme achieves a significant reduction in convergence time and an improvement in linearization accuracy in the presence of an unknown loopback delay. The experimental results in an FPGA prototyping platform show that the fast adaptation speed enables the predistorter to track time-varying PA nonlinearities as fast as in the tens of kilohertz range, constituting a potential solution for highly efficient PAs in mobile handsets.

In this paper, we propose a hybrid domain framework to model the predistorter (PD) of a power amplifier (PA). It is available for obtaining the PD not only through a PA model but also a PA circuit on ADS. Simulation results show that with predistortion, the NMSE of the linearity can reach -50 dB and the ACPR can reduce around 17dB. What's more, a processing unit is designed to work with the PD, so that the PD's coefficients can adjust to the changes of the PA adaptively, making the PA perform great linear in the transmitter system. The proposed framework is a helpful guidance for the design of circuits.

Recently, many papers have been published on the designs of predistortion systems for power amplifiers (PA). Most of these studies are based on computer simulations. In this work, we examine our predistorter (PD) designs on a practical microwave PA in a laboratory setup. The objective is to validate two PDs of different design approaches. The first PD is modeled using a simplicial canonical piecewise linear (SCPWL) function while the second one is modeled using a polynomial function. The former exploits the properties of the SCPWL function to develop a reduced complexity PD identification method. The latter utilizes the secant method to iteratively search for the signal at the PD output, thus parameter identification is avoided. The implementation complexity and effectiveness of the PDs are compared. The limitations of the measurement system for predistorter design is also discussed briefly

FPGA (Field Programmable Gate Arrays) implementation of an off-line handwritten digit recognition system based on elastic meshing directional feature extraction and integrated neural network classifier is proposed in this paper. Elastic meshing directional feature extraction is used to extract the feature of normalized 32*16 handwritten digit images. Integrated neural network classifier with BP (back-propagation) learning algorithm is designed as classifier. The pipeline technology and multi-buffer technology are used in the FPGA implementation of elastic meshing directional feature extraction. FPGA implementation architecture of neural network computing unit and integrated neural network classifier is proposed in this paper. Experiment shows that compared with software-based implementation, FPGA-based system can greatly speed up off-line handwritten digit recognition and is suitable for application in some real-time situations where high process speed and portability are required.

Characterisation of the standard deviation of a time‐series signal has uncommon, yet widespread applications. The usual requirement for a representation of signal standard deviation in real‐time implies a high computation speed. A method based on a field programmable gate array (FPGA) implementation is presented. The technique is benchmarked against conventional computational approaches and shows a single windowed standard deviation update calculation of a 16 bit sample can be achieved in 11 ns on a modern CPU. The FPGA implementation is found to be superior to all other approaches examined with an operation time of below 10 ns, and thus provides a useful tool for the real‐time measurement of the standard deviation of signals above 100 MHz.