Proving finite state machines correct with an automaton-based method

Many-core accelerator chips are becoming increasingly popular these days for its high performance floating-point performance exceeding 1 Tflops per chip. Aho-Corasick (AC) is a multiple patterns string matching algorithm commonly used in computer and network security, bioinformatics, among others. In order to simultaneously match a number of string patterns with respect to the input text data, a Deterministic Finite Automata (DFA) is constructed from a given set of pattern strings. The DFA is referenced almost randomly, whereas the input data is sequentially accessed. As the number of pattern strings increases, the irregular DFA accesses lead to poor cache locality and low overall performance. In this paper, we present a cache locality optimizing parallelization on the many-core accelerator chip, the Intel Xeon Phi. A given set of pattern strings is partitioned into into multiple sets of a smaller number of patterns so that multiple small DFAs are constructed instead of single large DFA. The accesses to multiple small DFAs lead to significantly smaller cache footprints in each core's cache and result in impressive performance improvements. Experimental results on the Intel Xeon Phi 5110P show that our approach delivers up to 2.00 × speedup compared with the previous approach using single large DFA.

Deep Packet Inspection (DPI) technology has been widely deployed in Network Intrusion Detection System (NIDS) to detect attacks and viruses. State-of-the-art NIDS uses Deterministic Finite Automata (DFA) to perform regular expression matching for its stable matching speed. However, traditional DFA algorithm’s throughput is limited by the input character’s width (usually one character per time). In this paper, we present an architecture named Parallel-DFA to accelerate regular expression matching by scanning multiple characters per time. Experimental results show that, our architecture can achieve as high as 1200 Gbps (1.17 Tbps) rate on current single Field-Programmable Gate Array (FPGA) chip. This makes it a very practical solution for NIDS in 100G Ethernet standard network, which is currently the fastest approved standard of Ethernet. To the best of our knowledge, this is the fastest matching performance architecture on a single FPGA chip. Besides, the throughput is nearly 3 orders of magnitude (916\(\times \)) than that of original DFA implemented on software. Our architecture is about 183.2\(\times \) efficiency than that of original DFA.

Synthesis techniques for temporal logic specifications are typically based on exploiting symbolic techniques, as done in model checking. These symbolic techniques typically use backward fixpoint computation. Planning, which can be seen as a specific form of synthesis, is a witness of the success of forward search approaches. In this paper, we develop a forward-search approach to full-fledged Linear Temporal Logic on finite traces (LTLf) synthesis. We show how to compute the Deterministic Finite Automaton (DFA) of an LTLf formula on-the-fly, while performing an adversarial forward search towards the final states, by considering the DFA as a sort of AND-OR graph. Our approach is characterized by branching on suitable propositional formulas, instead of individual evaluations, hence radically reducing the branching factor of the search space. Specifically, we take advantage of techniques developed for knowledge compilation, such as Sentential Decision Diagrams (SDDs), to implement the approach efficiently.

Intelligent and efficient grouping algorithms for large-scale regular expressions

Deep Packet Inspection (DPI) systems have been becoming an important element in traffic measurement ever since port-based classification was deemed no longer appropriate, due to protocol tunneling and misuses of well-defined ports. Current DPI systems express application signatures using regular expressions and it is usual to perform pattern matching through the use of Finite Automaton (FA). Although DPI systems are essentially more accurate, they are also resource-intensive and do not scale well with link speeds. Looking to this area of interest, this paper proposes a novel Deterministic Finite Automaton, called Ranged Compressed Deterministic Finite Automaton (RCDFA), that compresses transitions without additional memory lookups. Experimental results show that RCDFA yields space savings of 97% over the original DFA and up to 93% better compression when compared to the DFA's state-of-the-art compression techniques.

We present a symmetric-key predicate-only functional encryption system, SP-FE, which supports functionality for regular languages described by deterministic finite automata. In SP-FE, a data owner can encrypt a string of symbols as encrypted symbols for matching. Later, the data owner can generate predicate tokens of the transitions in a deterministic finite automaton (DFA). The server with these tokens can decrypt a sequence of encrypted symbols correctly and transfer from one state to another accordingly. If the final state belongs to the set of accept states, the server takes assigned operations or returns the corresponding encrypted data. We have proven SP-FE preserves both keyword privacy and predicate privacy through security analysis and security games. However, to achieve predicate privacy, we put bounds on the length of a keyword and the number of states of a DFA. Due to these restrictions, SP-FE can only capture finite languages. Finally, we present the performance analysis of SP-FE and mention possible future work.

We present a parallel algorithm for the minimization of deterministic finite state automata (DFAs) and discuss its implementation on a connection machine CM-5 using data parallel and message passing models. We show that its time complexity on a p processor EREW PRAM (p/spl les/n) for inputs of size n is O([n log/sup 2/ n/p]+log n log p) uniformly on almost all instances. The work done by our algorithm is thus within a factor of O(log n) of the best known sequential algorithm. The space used by our algorithm is linear in the input size. The actual resource requirements of our implementations are consistent with these estimates. Although parallel algorithms have been proposed for this problem in the past, they are not practical. We discuss the implementation details and the experimental results.

The problem of approximate string searching comprises two classes of problems: string searching with k mismatches and string searching with k differences. In this paper we present a short survey and experimental results for well known sequential approximate string searching algorithms. We consider algorithms based on different approaches including dynamic programming, deterministic finite automata, filtering, counting and bit parallelism. We compare these algorithms in terms of running time against pattern length and for several values of k for four different kinds of text: binary alphabet, alphabet of size 8, English alphabet and DNA alphabet. Finally, we compare the experimental results of the algorithms with their theoretical complexities.

Don't-care conditions are utilized by many synthesis tools because such conditions provide additional flexibility for logic optimization. However, most techniques only focus on the gate level because it is difficult to handle such conditions accurately at behavior and register transfer levels. This is problematic since the trend is to move toward high-level synthesis. In this paper, we propose innovative methods to handle such conditions accurately at high-level designs. In addition, we propose three novel algorithms based on our new methods to minimize the number of registers that need to be initialized, which can reduce the routing resources used by the reset signals and alleviate the routing problem. We applied our techniques to a five-stage pipelined processor and successfully reduced the number of control registers that need to be initialized by 53%, demonstrating the effectiveness of our approach.

Runtime verification is a lightweight verification structure with the advantages of formal verification and software testing. In this paper, we studied JavaMOP that is an instance of the MOP (monitoring oriented programming) runtime verification structure. In the LTL plugin of JavaMOP, the LTL formula was translated into a nondeterministic buchi automaton (NBA) and then the NBA was translated into a deterministic finite automaton (DFA). While in the translation process, the number of states of the automata could increase exponentially. So we first use a procedure to remove the redundant states in the NBA, then we use an algorithm based on fair simulation which was used in model checking to further simplify the NBA. Experimental results show that the memory usage at runtime of JavaMOP can be reduced.

The Rapid growth of internet resulted in feature rich and dynamic web applications. This increase in features also introduced completely under estimated attack vectors. Cross site scripting attacks, SQL Injection and malicious file execution are the most dominant classes of web vulnerabilities reported by OWASP 2011. These attacks make use of vulnerabilities in the code of web applications, resulting in serious consequences, such as theft of cookies, passwords and other personal credentials. It is caused by scripts, which do not sanitize user input. Several server-side counter measures for XSS attacks do exist, but such techniques have not been universally applied, because of their deployment overhead. The existing client-side solutions degrade the performance of client's system resulting in a poor web surfing experience. We present automata-based symbolic string analyses (XHunter)for automatic verification of string manipulating programs we compute the pre and post conditions of common string functions using deterministic finite automata (DFAs). Experiment result shows that our approach finds large number of malicious attacks in web application.

In order to fill the PEP and SPEAR storage rings with beams from the SLC (Stanford Linear Collider) linac and damping rings, precise control of the linac subharmonic buncher and the damping ring RF is required. Resettable GaAs master/slave D-type flip-flops have recently been developed which are capable of operating at frequencies of 3 GHz and higher. Using these digital devices as frequency dividers, one can phase-shift the SLAC (Stanford Linear Accelerator Center) continuous-wave (CW) RF systems to optimize the timing for filling the storage rings. The performance of integrated circuits from two vendors was evaluated for this application. Using microstrip circuit techniques, the authors built and operated in the accelerator several chassis to synchronize a reset signal from the storage rings to the SLAC 2.856-GHz RF and to phase-shift divide-by-four and divide-by-sixteen frequency dividers to the nearest 350-ps bucket required for filling.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multispectral image fusion based on fractal features

Temperature cycling, alongside Viedma ripening, has been established as a reliable method for deracemizing racemic mixtures of chiral compounds that crystallize as a conglomerate. Here we report that the speed of temperature cycling can be increased by using chiral additives. We also demonstrate that the chirality of the additive determines the final enantiomeric state of the solid phase. Viedma ripening experiments using equivalent conditions, with and without chiral additives, are always found to be slower.

The main purpose of this work is to build classically stationary bubbles, within the thin-shell formalism, which are unstable under quantum effects; they either collapse into a black hole or expand. Thus, the final state can be thought of a superposition of geometries. We point out that, from a quantum mechanical point of view, there is no issue with a loss of information in such configuration. A classical observer sees a definite geometry and, hence, finds an effective loss of information. Although it does not cover all possible cases, we emphasise the role of semi-classical gravitational effects, mediated by instatons, in alleviating/solving the information loss paradox.