Quadrature bandpass ΔΣ modulation for digital radio

This paper presents a study of the effects of the op-amps' finite DC-gain (FDCG) and nonlinear DC-gain (NLDCG) on switched-capacitor (SC) delta-sigma (/spl Delta//spl Sigma/) modulators. Starting with the theoretical point of view, these two nonidealities are analytically studied, modeled and their effects on the overall signal to noise plus distortion ratio (SNDR) of a modulator are discussed. Several simulations are performed to clarify the various effects of FDCG and NLDCG on a typical single loop modulator. It is shown that although FDCG of the first stage of the modulators has always attracted the most concerns on /spl Delta//spl Sigma/ literature, NLDCG of the first stage could have a worse effect in the output SNDR due to its nonlinear nature which directly manifests itself as a distortion error and increases the in-band noise of the modulator.

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.

Given an integer /spl sigma/>1, a vector (/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/), of nonnegative integers, and an undirected graph G=(V, E), an L(/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/)-coloring of G is a function f from the vertex set V to a set of nonnegative integers, such that |f(u)-f(v)|/spl ges//spl delta//sub i/, if d(u,v)=i, for 1<i<(/spl sigma/-1), where d(u, v) is the distance (i.e., the minimum number of edges) between the vertices u and v. An optimal L(/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/)-coloring for G is one using the smallest range /spl lambda/ of integers over all such colorings. This problem has relevant application in channel assignment for interference avoidance in wireless networks, where channels (i.e., colors) assigned to interfering stations (i.e., vertices) at distance i must be at least /spl delta//sub i/ apart, while the same channel can be reused in vertices whose distance is at least /spl sigma/. In particular, two versions of the coloring problem - L(2, 1, 1) and L(/spl delta//sub 1/, 1,..., 1) - are considered. Since these versions of the problem are NP-hard for general graphs, efficient algorithms for finding optimal colorings are provided for specific graphs modeling realistic wireless networks, including rings, bidimensional grids, and cellular grids.

In this paper, the design of a continuous-time baseband sigma-delta (/spl Sigma//spl Delta/) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF /spl Sigma//spl Delta/ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF /spl Sigma//spl Delta/ modulator is 0.2 mm/sup 2/ in 0.35-/spl mu/m CMOS.

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allows direct sampling of the RF signal, reducing analog hardware, and makes it easier to realize completely software programmable receivers. This paper presents the circuit design of and test results from a continuous time tunable IF sampling 4/sup th/ order bandpass delta-sigma modulator implemented in InP HBT IC technology for use in a multi-mode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The 4/sup th/ order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wideband and narrowband operation. The IF is tunable from 140 MHz to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5 V power supplies, the fabricated 4/sup th/ order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal to (noise+distortion) ratio (SNDR) of 78 dB @ 1 MHz BW and 50 dB @ 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB @ 1 MHz BW and 47.7 dB @ 60 MHz BW.

Let /spl delta//sub /spl Sigma// be a measure of the relative stability of a stable dynamical system /spl Sigma/. Let /spl tau//sub A(/spl Sigma//) be a measure of the computational efficiency of a particular algorithm A which verifies the stability property of /spl Sigma/. For two representative cases of /spl Sigma/, we demonstrate the existence of a particular measure /spl delta//sub /spl Sigma// and an algorithm A such that, /spl delta//sub /spl Sigma///spl tau//sub A(/spl Sigma//)=c where c depends possibly on the dimension of the system /spl Sigma/ and parameters which are specific to the algorithm A, but independent of any other system characteristics. In particular, given /spl Sigma/ and A, one can estimate /spl delta//spl Sigma/ by measuring /spl tau//sub A(/spl Sigma//).

We present an integrable solution for the detection of defective sensor elements using sigma-delta-(/spl Sigma//spl Delta/)-modulation and a matched filter. The sensor element is stimulated using a pseudo random binary sequence (PRBS). The sensor signal is read out and the analog output is digitized using a /spl Sigma//spl Delta/-modulator. The binary pulse density stream of the /spl Sigma//spl Delta/-modulator is the output of the sensor system and thus should ideally contain the PRBS. A matched filter has the task of detecting the pseudo random sequence in the pulse density stream and its sampled output is compared to a threshold thus making it possible to judge the functionality of the sensor element. By evaluating the magnitude of the matched filter output it is also possible to measure the sensor sensitivity. We present a discrete solution of this method, but an integrated chip using a standard 1.2 /spl mu/m CMOS process has been designed and is being fabricated.

A technique for shaping component mismatch error in the real and imaginary paths of a complex (quadrature) /spl Delta//spl Sigma/ are studied and simulated. Complex bandpass /spl Delta//spl Sigma/ modulators provide improved performance over a pair of real bandpass /spl Delta//spl Sigma/ modulators of the same order in the conversion of narrow-band quadrature intermediate frequency (IF) signals. This is possible due to elimination of redundant conjugate pairs of poles and zeros in its noise and signal transfer function. Mismatches in the modulators real and imaginary paths, however, results in spectral leakage of image band interference and image band quantization noise to the passband of the converted output. Strategic pole-zero placement, as well as adaptive techniques has been studied in earlier works. The work presented here takes advantage of the inherent dual paths of the complex bandpass /spl Delta//spl Sigma/ modulator to reduce component mismatch effects using a switched capacitor error shaping technique.

An ultra low power second-order switched capacitor (SC) sigma-delta (/spl Sigma//spl Delta/) modulator is presented. Using of a class-C inverter instead of an operational transconductance amplifier (OTA) enables the SC /spl Sigma//spl Delta/ modulator to achieve sub-/spl mu/W power consumption. The proposed modulator has been implemented using a 0.35/spl mu/m CMOS process. The measured peak SNR of the modulator is 56dB in a 3kHz signal bandwidth with sampling frequency of 200kHz. Its dynamic range is approximately 56 dB and the power consumption is only 0.8/spl mu/W with a 1V power supply.

Using oversampled sigma-delta (/spl Sigma/-/spl Delta/) techniques a signal can be represented as a single bit binary data stream ({-1, 1}), with the quantization noise high pass filtered out of baseband. In this paper adaptive LMS digital filters are presented that directly use binary /spl Sigma/-/spl Delta/ input streams and update the PCM adaptive filter weights at the oversampled rate to realize architectures that are very suitable for mixed analog/digital VLSI implementation. Using the /spl Sigma/-/spl Delta/ adaptive architecture PCM values are multiplied by single bits, and can therefore be easily performed by a simple multiplexor. Also using the /spl Sigma/-/spl Delta/ approach, the decimation and interpolation stages required for converting from /spl Sigma/-/spl Delta/ to PCM (and vice-versa) suitable for Nyquist DSP algorithms are circumvented. The paper describes the sigma delta adaptive LMS filter architecture and presents preliminary results for adaptive echo cancellation using adaptive sigma delta and standard PCM architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The design of a low-voltage and low-power /spl Delta//spl Sigma/ analog-to-digital (A/D) converter is presented. A third-order single-loop /spl Delta//spl Sigma/ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV /spl Delta//spl Sigma/ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-/spl mu/W power consumption.

The design of a delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for direct voltage readout of an electret microphone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged together with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourth-order /spl Delta//spl Sigma/ ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise+distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumentation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A combined continuous-time/switched-capacitor design is used to minimize power consumption.

This paper presents an investigation of the performance characteristics of a pair of bandpass Sigma-Delta (/spl Sigma/-/spl Delta/) analog-to-digital (A/D) converters. One of these /spl Sigma/-/spl Delta/ A/D converters has the conventional cascade-of-integrators structure while the other has the conventional cascade-of-resonators structure. These /spl Sigma/-/spl Delta/ A/D converters are subsequently compared in terms of their achievable signal-to-quantization noise ratios for corresponding (discrete) switched-capacitor implementations. Based on this comparison, a new bandpass /spl Sigma/-/spl Delta/ A/D converter structure is proposed which possesses the best practical features of both converters. These include, complementary signal and noise transfer functions and the fact that the zeros of the noise transfer function are constrained to lie on the unit-circle.

It is well known that /spl Sigma/-/spl Delta/ A/D converters having complementary signal and noise transfer functions exhibit high signal-to-quantization-noise ratios (SQNRs) and high dynamic ranges (DRs), but that they tend to be overly sensitive to capacitor mismatches (potentially leading to unstable converter operation) in a corresponding switched-capacitor (SC) hardware implementation. Recently, a new class of /spl Sigma/-/spl Delta/ A/D converters was developed based on magnitude-squared or magnitude complementary signal and noise transfer functions to decrease the sensitivity to capacitor mismatches at the expense of slightly lower SQNRs and DRs. This paper is concerned with the development of a novel approach to the design of /spl Sigma/-/spl Delta/ A/D converters. This approach combines the transfer function complementarity (in the overall frequency band) with signal and noise transfer function magnitude complementarity (in the signal passband) to obtain a single /spl Sigma/-/spl Delta/ A/D converter with a cascade-of-resonators configuration. Consequently, the resulting A/D converters achieve not only high-stability (arising from magnitude complementarity), but also high DR and SQNR (arising from transfer function complementarity) in the SC hardware implementation. A practical application example is given to illustrate the results.

We present novel oversampled implementations of adaptive LMS FIR filters using sigma delta (/spl Sigma//spl Delta/) computation strategies. Using this approach in conjunction with /spl Sigma//spl Delta/ DACs and ADCs the need for expensive decimation and interpolation stages for the /spl Sigma//spl Delta/ codec has been circumvented. Hence the complete architecture can make considerable savings in total silicon area for a mixed signal ASIC implementation. The LMS algorithm performance of the /spl Sigma//spl Delta/ approach is shown to be comparable to the traditional Nyquist rate PCM LMS algorithm.