Quantum types: going beyond qubits and quantum gates

Biomolecular residue pairs have been utilized in constructing quantum logic gates (QLGs), significantly reducing the hardware size to the subnanoscale level. However, the development of molecular fault-tolerant topological quantum computers (TQCs) presents challenges in error reduction and hardware size minimization. This study presents the manipulation of molecular QLGs (MQLGs) by utilizing protein residue pairs as molecular transistors, enabling the construction of molecular topological QLGs. This innovative approach leverages molecular functionality in quantum computer (QC) designs to build sub-nanometer transistors that significantly reduce size, enhance efficiency, and accelerate computing. The transmission spectra of electron transfer in molecular junction systems were analyzed using the non-equilibrium Green’s function method. The molecular field effect led to the observation of four quantum states on a two-dimensional potential energy surface with two degrees of freedom—proton translation and molecular rotation. These states form a quaternary QLG, similar to a 2-qubit controlled-NOT logic gate. By applying the Kitaev honeycomb lattice model, MQLGs were employed to generate nonabelian anyons that adhere to fusion rules, such as Ising and Fibonacci anyons. Furthermore, quantum circuits incorporating nonabelian anyons and their fusion processes were developed for practical applications. These findings underscore the shift away from conventional atom-based silicon technology and highlight the potential for innovative applications of molecular universal QLGs, particularly in the advancement of sub-nanometer molecular fault-tolerance TQCs.

Quantum Gates and Quantum Circuits of Stock Portfolio

Non-adiabatic holonomic quantum gate in decoherence-free subspaces is of greatly practical importance due to its built-in fault tolerance, coherence stabilization virtues, and short run-time. Here, we propose some compact schemes to implement two- and three-qubit controlled unitary quantum gates and Fredkin gate. For the controlled unitary quantum gates, the unitary operator acting on the target qubit is an arbitrary single-qubit gate operation. The controlled quantum gates can be directly implemented by utilizing non-adiabatic holonomy in decoherence-free subspaces and the required resource for the decoherence-free subspace encoding is minimal by using only two neighboring physical qubits undergoing collective dephasing to encode a logical qubit.

The major trouble at present time technology is the information loss due to high technology circuits and system designed using irreversible hardware, to solve this problem used quantum gate. The prime purposed of designing quantum gate to reduce power consumption, decrease quantum cost, delay, number of garbage outputs. Quantum gate requires non-demolition of information, Therefore the number of inputs must be similar to the number of outputs. This paper presents a review of the asynchronous counter designed by T flip-flop and comparing with existing.

To employ a quantum device, the performance of the quantum gates in the device needs to be evaluated first. Since the dimensionality of a quantum gate grows exponentially with the number of qubits, evaluating the performance of a quantum gate is a challenging task. Recently, a scheme called quantum gate verification (QGV) has been proposed, which can verifies quantum gates with near-optimal efficiency. In this paper, we implement a proof-of-principle optical experiment to demonstrate this QGV scheme. We show that for a single-qubit quantum gate, only $\ensuremath{\sim}300$ samples are needed to confirm the fidelity of the quantum gate to be, at least, 97% with a 99% confidence level using the QGV method, whereas, at least, $\ensuremath{\sim}3000$ samples are needed to achieve the same result using the standard quantum process tomography method. The QGV method validated by this paper has the potential to be widely used for the evaluation of quantum devices in various quantum information applications.

In order to fulfill quantum information processing tasks such as quantum computation and scalable quantum networks, quantum logic gates are indispensable parts. A multiqubit logic gate can efficiently reduce the cost of physical resources and complicated operations that are necessary in the combination of fewer‐qubit (e.g., two‐qubit) logic gates to fulfill the same tasks. However, the construction of multiphoton quantum logic gates is a large challenge. Assisted by spatial and temporal degrees of freedom, a polarization multiphoton controlled one‐photon unitary gate is proposed, which can be realized with three processes including the control‐path process based on weak cross‐Kerr nonlinearities, the unitary transformation process, and the output process. In the control‐path process, the control‐path modules are applied, where the entanglement between polarization, spatial and temporal degrees of freedom is generated by beam splitters, time delayers, and nonlinear interaction in cross‐Kerr media. The scheme presented here, assisted by spatial and temporal degrees of freedom reduces the experimental complexity of the schemes assisted by only spatial degree of freedom. Moreover, it will also be a useful reference in optimally constructing multiqubit quantum logic gates with other multiple degrees of freedom in many physical systems.

In order to improve the training efficiency of the support vector machine, a quantum circuit training scheme based on the inner product of the quantum state for the support vector machine is proposed in this work. Firstly, on the basis of the full analysis of the computational complexity of the classical support vector machine, the kernel function which is the main factor affecting the computational complexity of the algorithm is primarily analyzed. Based on quantum mechanics and quantum computing theory, the training sample elements in the kernel function are quantized to generate the corresponding quantum states. Secondly, according to the quantum states of the training sample elements, the types and quantities of the required quantum logic gates are derived and calculated, and the quantum circuit that can generate the corresponding quantum states of the training sample elements through the evolution of the quantum initial ground states and the quantum logic gates is designed. Then, in the light of the relationship between the inner product of the quantum state and the quantum logic gate SWAP, the quantum circuit is designed to complete the exchange operation of the corresponding quantum state amplitude. The inner product of the quantum state is realized by exchanging and evolving the amplitude of the quantum state in the quantum circuit. Finally, by measuring the quantum state of the controlling qubit, the inner product solution of the kernel function is obtained, and the acceleration effect of training support vector machine is realized. The verification results show that the scheme enables the support vector machine not only to complete the correct classification, but also to operate the quantum part of the scheme on the real quantum computer . Compared with the classical algorithm, the scheme reduces the time complexity of the algorithm for the polynomial degree, greatly shortens the training time of the model, and improves the efficiency of the algorithm. The scheme has certain feasibility, effectiveness and innovation, and expands the training idea of the support vector machine.

This paper discusses the properties of Quantum bit (Qubit) and Quantum logic gates (Quantum not-gate, Hadamard gate and Quantum controlled not-gate etc.) by the generating element of Pauli algebra (Clifford algebra Cl3).

A simple scheme for a universal two-bit quantum logic gate is proposed. The scheme uses well defined atomic center-of-mass momentum states interacting with a resonant cavity field in Bragg regime. The cavity field state controls the atomic momentum state while passing through the cavity. The cavity field state acting as controller logic bit and the atomic momentum state as controlled logic bit together perform as a universal quantum logic gate.

A system of particles in a double well potential is a widely studied and useful example for understanding quantum mechanics. This simple system has recently been used in theoretical proposals and related experiments as a way to make quantum logic gates for ultracold atoms confined in optical lattices. Such quantum gates are the fundamental building blocks for quantum information processing; in these proposals, a regular array of cold atoms in an optical lattice serves as the quantum register. We explain how this research can be understood in terms of well-known principles for systems of identical particles.

Quantum computing plays a major role in modern computation. It can perform operations exponentially faster when compared to classical computation. It has applications in various areas like secure communication, drug design, artificial intelligence, cyber security, etc. Thus, the researchers and students are showing interest to perform experiments in quantum computing to design novel architectures. But to learn/understand quantum computing, one should have strong knowledge of its basics. Because quantum computing performs operations at the atomic level, so the learners need to understand basic concepts like Qubits, superposition, quantum gates, etc. This chapter gives a clear idea about the basic concepts of quantum computing like Qubits, superposition, entanglement, and quantum gates.

Recent progress in atomistic modelling and simulations of donor spin qubits in silicon

A new reversible Error Tolerant Adder (ETA) based on the reversible Logic is proposed. RH and RS gates are the novel reversible logic gates based on which the ETA is designed. The reversible 3×3 RH gate is derived from existing 2×2 quantum gates — CNOT, Controlled-V and Controlled-V+. The reversible 3×3 RS gate consists of the existing CNOT and Peres Quantum gates. The design of the proposed reversible ETA demonstrates better power delay product (PDP) than the existing ETA's in terms of quantum cost and delay, while maintaining the minimum number of garbage outputs. In comparison with other ETAs, the current design offers a PDP improvement of 54.06%.

We propose an approach to optimally synthesize quantum circuits from\nnon-permutative quantum gates such as Controlled-Square-Root-of-Not (i.e.\nControlled-V). Our approach reduces the synthesis problem to multiple-valued\noptimization and uses group theory. We devise a novel technique that transforms\nthe quantum logic synthesis problem from a multi-valued constrained\noptimization problem to a group permutation problem. The transformation enables\nus to utilize group theory to exploit the properties of the synthesis problem.\nAssuming a cost of one for each two-qubit gate, we found all reversible\ncircuits with quantum costs of 4, 5, 6, etc, and give another algorithm to\nrealize these reversible circuits with quantum gates.\n

In the noisy medium-scale quantum era, quantum computers are constrained by a limited number of qubits, restricted physical topological structures, and interference from environmental noise, making efficient and stable circuit scheduling a significant challenge. To improve the feasibility of quantum computing, it is essential to optimize the scheduling of quantum gates and the insertion of SWAP gates, reducing running time and enhancing computational efficiency. We propose a collaborative optimization framework that integrates the Quantum Exchange Lock Parallel Scheduler (QELPS) with the Full-level Joint Optimization SWAP Algorithm (FJOSA). In QELPS, SWAP conflict characteristics are used to adjust the layout of quantum gates across different levels while considering physical constraints and dynamically adapting to the circuit’s execution state. Quantum lock parallel technology enables the selective postponement of certain quantum gates, minimizing circuit depth and mitigating inefficiencies caused by excessive SWAP gate insertions. Meanwhile, FJOSA employs a cross-layer optimization strategy that combines heuristic algorithms with cost functions to improve gate scheduling at a global level. This approach effectively reduces quantum gate conflicts found in traditional methods and optimizes execution order, leading to better computational efficiency and circuit performance. Experimental results show that, compared to the traditional 2QAN algorithm, QELPS and FJOSA reduce additional gate insertions by 85.59% and 89.38%, respectively, while decreasing running time by 56.32% and 66.47%. These improvements confirm that the proposed method significantly enhances circuit scheduling efficiency and reduces resource consumption, making it a promising approach for optimizing quantum computation.