Real‐time digital multi‐function protection system on reconfigurable hardware

Directional overcurrent and earth-fault protections for a biomass microgrid system in Malaysia

This research focuses on the study of the directional phase overcurrent relaying concept that can be briefly explained by the relay tripping whenever the faulted current exceeds a pre-determined pick up value in a specific predefined direction, in order to isolate only the faulted part of the network. The Directional Phase Overcurrent Protection appears more important in the distribution system when the Overcurrent protection is the main protection. Any glitch in its setting can lead to opening the circuit in the non-faulty area or can perform non-trip in the faulty area. As an example in Algeria, this problem happens repeatedly in the plurality distribution substations. This reliable and selective protection is generally used in multisource networks, parallel transmission lines and mesh distribution networks. It is mainly characterized by its Maximum Torque Angle and Relay Characteristic Angle (RCA), also known as the directional angle as it decides the direction of the tripping zone. The variation of the RCA setting has a direct impact on the sensitivity operation of the relay (45 degrees' maximum sensitivity operation for any type of fault). Tests have been performed on The Four Step Directional Phase Overcurrent Protection Function of the Line Distance Protection REL670 ABB IED numerical relay. On one hand, the 51/67 ANSI protection has been tested and results were discussed. On the other hand, different cases of RCA settings were evaluated under fault to showcase that the 45-degree angle is the best applicable value for a maximum sensitivity.

A pilot-based distance protection scheme for meshed distribution systems with distributed generation

This paper presents a scheme of distance protection for a renewable energy plant in electric power distribution systems. In many developing countries where renewable energy power plants are typically located in rural remote areas, they must be connected to weak power distribution systems inevitably. Although over-current relays are used to protect feeders at substations, fuses are only available elsewhere along feeder lines. To secure the system operation, distance protection is assigned to protect feeders. In this paper, distance relays are placed in the feeder along with over-current relays and fuses. Design of the distance protection of multi-source systems is described. This study considered the system consisting of a renewable energy plant. The power plant was a 6-MW unit of firmed power generation. The test feeder was simplified to be an equivalent four-bus test feeder for relaying purpose. Fault analysis in this paper was performed by using PowerWorld™ software. Obtained fault currents were used to establish protective zones of distance relays. In addition, this paper also compared the result of using distance protection with those of using directional over-current protection. As a result, protection of the power feeder with renewable power plants by using distance relaying can reduce complication in relay setting due to the impedance-based setting of the distance relay.

The paper presents the procedure of directional ground overcurrent protection setting calculation in the transmission network by using classical calculation procedure and by using an advanced algorithm of differential evolution. To meet the basic requirements of relay protection systems such as speed, selectivity, coordination and sensitivity, the conditions that need to be considered when setting directional ground overcurrent protection are defined. By using the optimization method, the problem was solved in two ways. In the first case, the settings are designed to minimize the total response time of directional ground overcurrent protection to remote-end high-resistance faults, whereas in the second case the settings are designed so that the maximum response time to remote-end high-resistance fault is minimal. The results obtained using the classical approach are compared with the results obtained using the optimization method and the advantages and disadvantages of both approaches are highlighted.

Enhanced real time coordination of distance and user defined over current relays

Field Programmable Gate Arrays (FPGAs) provide flexible computational architectures that are ideal for digital signal processing (DSP). With support of a NIH/NIDCD SBIR grant, we are developing an open FPGA platform for the speech, hearing, and acoustics research communities. The advantage of using FPGAs in a computational platform over conventional CPU approaches is the ability to implement low-latency high-performance signal processing with deterministic latencies. The hardware portion of the platform includes an audio codec and an Intel System-on-Chip (SoC) FPGA that contains ARM CPUs alongside the computational fabric that allows custom data plane designs. Development uses Mathwork’s Simulink that allows exploration and simulation of signal processing algorithms. Once a Simulink model has been developed to implement audio processing in either the time domain or frequency domain, VHDL code can be generated that implements the desired signal processing. The VHDL code is then implemented in the FPGA computational fabric where the FPGA functions as a real-time signal processor. We are currently soliciting ideas/feedback from the speech, hearing, and acoustic communities as to what features they would like to see in the next iteration of the open FPGA-based computational platform. [NIH/NIDCD R44DC015443: www.openspeechtools.com]

Fault clearing time is critical to the safety of power system equipment. Most state-of-art distance relays operate at the speed of one cycle or even longer. There are a few sub-cycle algorithms such as half-cycle type Fourier, least error square, traveling wave, and wavelet type methods. This paper utilizes a sub-cycle (phaselet) method for estimation. The algorithm and testing with IEC 61850 Sampled Value and GOOSE communication protocols was discussed in detail in the recently accepted paper by the authors in the IEEE Transactions on Smart Grids [1]. The main focus of this paper is on the hardware implementation of the phaselet method on field programmable gate arrays (FPGAs) to achieve high speed and the hardware-in-the-loop testing. The FPGA implementation of the method helps in parallelizing the algorithm and provides fast computation speed compared to sequential execution on digital signal processor (DSP). The algorithm is implemented on Xilinx Virtex 6 board. The FPGA relay is tested using hardware-in-the-loop simulations with a real time digital simulator (RTDS).

Since 1988, the system relay engineer of Kansas Power & Light Gas Service has served as a guest lecturer for the course on fault analysis and protection of power systems at Kansas State University. He meets the class five times during the semester. Two of these visits are field trips. In the other three visits he discusses power systems protection from a practicing engineer's point of view. He also discuss a practical design problem prepared for this class. The details of the course, the design project, and other activities are described. The benefits of such cooperation between university and industry are outlined. The main objectives of this course are to: make the students familiar with symmetrical components and fault analysis; make the students familiar with computer methods for fault analysis; make the students familiar with directional overcurrent, differential, distance, and pilot protection; impart practical knowledge on protection to the students; are prepare students for projection-related jobs in the utilities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract Session: 2711 Teaching Hardware Design of Fixed-Point Digital Signal Processing Systems David V. Anderson1 and Tyson S. Hall2 1 Georgia Institute of Technology, Atlanta, GA 30332–0250, dva@ece.gatech.edu 2 Southern Adventist University, Collegedale, TN 37315–0370, tyson@southern.edu Abstract Signal processing theory and practice are enabling and driving forces behind multimedia de- vices, communications systems, and even such diverse fields as automotive and medical sys- tems. Over 90% of the signal processing systems on the market used fixed-point arithmetic because of the cost, power, and area savings that fixed-point systems provide. However, most colleges and universities do not teach or teach only a very little fixed-point signal process- ing. This issue is being addressed slowly around the country but now a new challenge or opportunity presents itself. As reconfigurable logic technology matures, field-programmable gate arrays (FPGAs) are increasingly used for signal processing systems. They have the ad- vantage of tremendous throughput, great flexibility, and system integration. The challenge is that signal processing in FPGAs is a much less constrained problem than signal processing in special purpose microprocessors. The opportunity arises in that it is now possible to explore more options and, more especially, to take a more systems-level approach to signal processing systems. In short, designing a signal processing system using FPGAs provides opportunities to look at many system design issues and trade-offs in a classroom setting. We have developed a course to teach signal processing in FPGAs at Georgia Institute of Technology and in this paper we consider the challenges and methods of teaching fixed- point system design in this course. We discuss the topics chosen and how they differ from traditional microprocessor-based courses. We also discuss how systems engineering concepts are woven into the course. 1 Motivation This paper describes the early development of a system design curriculum that uses field programmable gate arrays (FPGAs) to implement digital signal processing (DSP) systems. The goals of this curriculum are several-fold, including: • to prepare students for system design problems with which they are likely to be pre- sented upon graduation; Proceedings of the 2007 American Society for Engineering Education Annual Conference & Exposition Copyright c 2007, American Society for Engineering Education

This paper presents a design of non-directional overcurrent relay micro-controller-based having the advantages of low cost, high performance and can be totally manufactured by local manufacturers. The proposed overcurrent relay can be employed to protect feeders of distribution systems for overcurrent and earth fault protection. Also, the proposed relay is considered a high speed overcurrent relay, thus it can be used for restricted earth fault applications. The main hardware platform is designed and tested with pickup accuracy not more than 0.001In and total scan cycle not more than 1ms which make this relay very accurate and adequate for fast tripping applications. . The relay has the capability to treat the incoming analogue signals of voltages and currents via the Discrete Fourier Transform (DFT) through the designed main hardware platform. In this way if the relay protects a distribution power transformer, it can detect the inrush conditions via the second harmonic detection. Also it can detect the over excitation via the fifth harmonic calculations to block the abnormal tripping for more reliable and secure distribution systems.

Field Programmable Gate Arrays (FPGAs) are increasingly vital components of electronic systems used in numerous industries. FPGAs possess well-documented logic and hardware vulnerabilities that could allow an adversary to penetrate and manipulate FPGA-based electronic infrastructure. To detect such attacks against FPGA firmware, we developed a technique that exploits the unintended RF side-channel emitted from an FPGA. Our approach presumes that malicious modification to a trusted FPGA bitstream will result in changes in radio frequency (RF) emissions—changes that our technique can detect and measure using signal processing and machine learning. The development of our RF side-channel technique was divided into three tasks: (1) determine if firmware changes can be detected using side-channel emissions, (2) determine the minimum firmware change that can be detected, and (3) extend our approach to work across multiple devices of the same type. We used the Digilent Arty development board to accomplish these tasks. We developed baseline firmware for the board and then generated additional bitstreams that incorporated quantifiable changes in the logic and placement. We then collected RF side-channel emissions for each bitstream using the Riscure EM Probe Station, which uses a 1 GHz bandwidth near-field antenna. Using our RF side-channel approach, we were able to detect the movement of a single register or lookup table element by one slice. We proved the effectiveness of our technique to detect changes across multiple FPGAs of the same type by achieving detection accuracy greater than 98%.

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In this work, we propose a novel method of implementing an ultrafast ultrasound beamformer for plane wave imaging (PWI) on a field programmable gate array (FPGA). First, a modified delay calculation method was proposed to (1) separate the transmit and receive delay, (2) reduce the size of delay profile, and (3) enable parallel beamforming by delay reuse and data vectorization. Second, a parallelized implementation of beamformer on single FPGA was proposed by (1) loading pre-calculated delay profile from external memory instead of calculating delay on run-time, (2) vectorizing channel data fetching, (3) compensating transmit and receive delays separately, and (4) using fixed summing networks to reduce consumption of logic resources. The proposed method was also highly scalable, which was demonstrated by implementing the beamformer with different beamforming rates ranging from 2.4 G to 9.6 G samples per second to three different sizes of FPGAs ranging from entry-level FPGA to high-end FPGA. The power consumption was less than 3 watts for 2.4 G samples per second beamforming rate, which demonstrates the possibility of implementing ultrafast ultrasound imaging on handheld probe. The FPGA beamformer’s results were compared with Verasonics CPU beamformer’s result to verify that the image quality was not compromised for speed.

Design and implementation of a versatile digital directional overcurrent relay