Real‐Time Simulation Technologies in Engineering

This paper presents a digital implementation of 4-D autonomous hyperchaotic system on a Field Programmable Gate Array (FPGA) technology. In the design, the system parameters are selected according to the requirements for obtaining a hyperchaotic behavior. The hyperchaotic nature is theoretically verified by using bifurcation analysis and Lyapunov exponents’ calculus; and experimentally assessed by the FPGA implementation. A master-slave scheme for secure data transmission is used. Active control is applied to carry out the synchronization between the master and the slave. FPGA technology is applied in order to be implemented in digital form the 4-D continuous system using a XILINX VERTEX5 chip. The digital sequence generated from the FPGA device is observed in our experimental setup. The implementation with 32 bits fixed point is chosen; highlighting the role of synchronization mechanisms of chaotic systems in the success of these transmissions.

A new hardware platform for digital real-time simulation and control applications is introduced which is highly expandable and customizable due to its modular design and flexible, open interfaces. The system is based on digital signal processors (DSPs) and field programmable gate arrays (FPGAs). A detailed description of the processor and interface boards as core components of the system is given. A small-scale desktop system for hardware-in-the-loop real-time simulations is shown. Furthermore, modeling methodologies and commonly used integration techniques with regard to usual problems and practical implementation are presented. An actual implementation is presented as an example simulation which is used to verify the functionality and evaluate the performance of the real-time simulation platform. A real-time simulation of a buck converter with a time-step of 1 µs without FPGA co-processing is shown and the simulation results are compared to real hardware measurements. To address the common problem of inter time-step switching, solutions are discussed and two approaches are implemented and compared. In total, this paper presents a short overview of digital real-time simulation including modeling and integration, software implementation, hardware platform for code execution and hardware-in-the-loop testing.

The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

In this study, an ongoing Project named FPGA Based Digital Electronics Education (FPGA_b_DEEP) is introduced and the advantages of FPGA(Field Programmable Gate Arrays) technology which brought to digital design area are dealt with by using a case study. The Project aims to develop instructive and attractive examples to teach Digital Electronics efficiently and faster. In addition to this, PBL(Project Based Learning) method and Micro Learning method are dealt with at the study separately. PBL method has been used partially at the Project and the studies on Micro Learning for association with the Project are going on recently.

As Field programmable Gate Array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPCA technology. As this paper demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 5 MHz (with a clock rate of at least 40 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation. Distributed arithmetic was determined to be the most optimal structure for a FPGA FIR design, although future research may show that fast FIR algorithms or filtering in the frequency domain might give better results.

Testing battery pack configurations for their performance under different dynamic load profiles for grid and electric vehicle applications is expensive. Lowering the cost to understand the response of packs and their control strategies is critical. Power hardware in the loop (PHIL) simulation is widely used in power engineering for system and component testing. A simulator computes the model output in real-time, and then controls a power source to generate a dynamic power output with the expected current and voltage response of the emulated battery pack. This emulated battery pack power output can be coupled to a physical load to perform testing.1 Small time steps are useful to observe the transient response of the emulated battery when there is a sudden change in the load. PHIL simulations can also be useful to study the transient response of controllers and inverters present in the battery management system by connecting these devices to the simulator. PHIL simulations can be used to test the model’s accuracy2, to conduct repeatability experiments and to test battery performance under extreme conditions without compromising on safety.3 It provides an efficient approach to designing and testing new configurations of batteries from data of a single cell without building their real prototypes. The computational speed required to solve the battery models chosen for PHIL simulations must be fast in order to achieve real-time implementation. Therefore, models chosen for these simulations tend to have less complexity. However, to provide a better understanding of a battery’s response under a specific load profile, it is necessary to use a model that that accurately represents the behavior of a real battery. Real-time simulations for physics-based battery models have been explored in the past.4 , 5 , 6 It is also essential to comprehend how different battery architectures and how aging affects the overall performance. In literature, equivalent circuit models that describe charge transfer and diffusion dynamics have been used as the main way to capture battery dynamics.7 , 8 We first show results generated using SIMULINK equivalent circuit models that are compiled to run fast on our Opal-RT real-time simulator. The Opal-RT simulator drives an AMETEK 40 kW power supply with feedback to the model, enabling an emulated battery pack response capable of 10ms dynamic control. We evaluate pack configurations with physical parameters that correspond to either LCO or NMC 18650 cells. Overall, this represents a 400V, 10kW pack. A programmable load is used to modulate the emulated battery pack and monitor its dynamic response. We further explore implementing single particle models with our PHIL simulations to help understand the internal dynamics of the cell captured by these models. Physics-based models have rarely been used for PHIL. Our results show that the PHIL emulation of the battery pack meets the expectations for the battery dynamics. However, we observe high frequency noise in the output signal of the emulated battery pack. Because this level of noise is not a trait present in real battery packs, we are exploring signal processing methods to filter and remove it, while retaining the essential dynamics of the emulated battery pack. References A. Viehweider, G. Lauss, and L. Felix, Simul. Model. Pract. Theory, 19, 1699–1708 (2011).Y. He, W. Liu, and B. J. Koch, J. Power Sources, 195, 2969–2974 (2010).H. Dai, X. Zhang, X. Wei, Z. Sun, J. Wang, and F. Hu, Electr. Power Energy Syst., 52, 174–184 (2013).P. W. C. Northrop, V. Ramadesigan, S. De, and V. R. Subramanian, J. Electrochem. Soc., 158, A1461 (2011).V. R. Subramanian, V. Boovaragavan, V. Ramadesigan, and M. Arabandi, J. Electrochem. Soc., 156, A260 (2009).P. W. C. Northrop, V. Suthar, Bharatkumar Ramadesigan, S. Santhanagopalan, R. D. Braatz, and V. R. Subramanian, J. Electrochem. Soc., 161, E3149 (2014).J. V. Barreras, C. Fleischer, A. E. Christensen, M. Swierczynski, E. Schaltz, S. J. Andreasen, and D. U. Sauer, IEEE Trans. Ind. Appl., 52, 5086–5099 (2016).H. Song, T. Kim, J. Jeong, B. Kim, D. Shin, B. Lee, and H. Heo, IET Power Electron., 6, 417–424 (2013).

The High Performance Computing (HPC-I) payload is an innovative computing device designed for deployment on the Australian scientific mission satellite FedSat. HPC-I will validate and evaluate the practicality of using reconfigurable field programmable gate array (FPGA) technology in the space environment. The deployment of reconfigurable FPGA technology on-board satellites is a very promising solution for digital signal processing in the challenging space environment, offering tremendous flexibility to adapt to changing operation requirements, while achieving very high performance. Such combined flexibility and performance is not found in conventional signal processing architectures. This paper presents the design and implementation on HPC-I of two common digital signal filtering algorithms, a 4-tap low pass FIR filter and a 32-tap moving average filter. The flexibility and adaptability of the system is discussed in the context of more complex functionality and changing operation requirements.

With the continuous development of The Times and technology, artificial intelligence algorithm and AI technology based on Field Programmable Gate Array (FPGA) technology have been widely used in people's life. This paper introduces the extensive application of artificial intelligence technology in production and life in recent years and its challenges. In view of the complexity of AI algorithm operation, real-time requirements and fast update and iteration characteristics, this paper proposes that FPGA chip can better solve these problems. This paper introduces the working principle of FPGA chip to realize digital processing and other hardware resources in detail, and analyzes the application advantages of FPGA in AI industry, life, and engineering. Compared with other chips, FPGA has the characteristics of low cost and flexible implementation of new algorithms, to achieve the balance between performance and cost. Finally, this paper summarizes the advantages of FPGA compared with other chips, and puts forward the possible development way and development platform in the future.

In the image and video processing field of mobile devices, edge detection is a fundamental technique for image segmentation, feature extraction and object tracking. Due to its high computational time in software implementation, we need to find a more efficient hardware approach to improve edge detection performance. With the development of Field Programmable Gate Array (FPGA) technology, the real-time parallel processing of huge video data stream using FPGA can be implemented because of FPGA reconfigurable and dedicated structure. In this paper, we present a FPGA-based implementation of edge detection technique for real-time pattern recognition applications and parallel processing. We propose a unique structure of Sobel Edge Detection on FPGA, which can significantly reduce the processing delay and improve the processing performance. The design is proved to be effective for real-time edge detection.

Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is to design prototype of an input/output port with handshaking capability using Field Programmable Gate Array (FPGA). The main reason of using the FPGA technology is it has unlimited number reprogrammed, cuts developing cost and development time. Xilinx Foundation 2.1i Series software in VHDL description was used as a development tool in this project. The VHDL codes were assimilated into a design and development atmosphere to accomplish many subtasks such as FPGA synthesis, optimization, placement, and routing. The successful design was translated, mapped, routed, and placed onto FPGA Demo Board. XC4010XLPC84 Xilinx FPGA from XC4000XL family was used as a target board. In prototype design, the FPGA pins were connected to a parallel printer port by using a coupled 25-pin DB connector, with a 36-pin Centronics connector cable. The output signals were observed and analyzed by using a logic analyzer.

The new generation of field programmable gate array(FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip(SOPC) developing environment. Therefore, this study presents a speed control integrated circuit(IC) for stepping motor drive under this SOPC environment. The design, using FPGA of Spartan-3E series, has realized a subdivision-variation control system for stepping motor. The bottom-top design method is applied in this study. The scheme integrates the current-feedback SPWM principle, the PI regulating technique, the closed-loop control and EDA design technology. The problem of high-subdivision stepping angle is solved effectively. Experimental results indicate that the control system can improve the control precision of stepping motor and make it run more smoothly.

Correlation has a variety of applications that require signal processing. However, it is computationally intensive, and software correlators require high-performance processors for real-time data analysis. This is a challenge for embedded devices because of the limitation of computing resources. Hardware correlators that use Field Programmable Gate Array (FPGA) technology can significantly boost computational power and bridge the gap between the need for high-performance computing and the limited processing power available in embedded devices. This paper presents a detailed FPGA-based correlator design at the register level along with the open-source Very High-Speed Integrated Circuit Hardware Description Language (VHDL) code. It includes base modules for linear and multi-tau correlators of varying sizes. Every module implements a simple and unified data interface for easy integration with standard and publicly available FPGA modules. Eighty-lag linear and multi-tau correlators were built for validation of the design. Three input data sets—constant signal, pulse signal, and sine signal—were used to test the accuracy of the correlators. The results from the FPGA correlators were compared against the outputs of equivalent software correlators and validated with the corresponding theoretical values. The FPGA correlators returned results identical to those from the software references for all tested data sets and were proven to be equivalent to their software counterparts. Their computation speed is at least 85,000 times faster than the software correlators running on a Xilinx MicroBlaze processor. The FPGA correlator can be easily implemented, especially on System on a Chip (SoC) integrated circuits that have processor cores and FPGA fabric. It is the ideal component for device-on-chip solutions in biosensing.

Field Programmable Gate Array (FPGA) technology is rapidly gaining traction in a wide range of applications. Nonetheless, FPGAs still require long design and debug cycles. To debug hardware circuits, trace-based instrumentation is inserted into the design that enables capturing data during the circuit execution into on-chip memories for later offline analysis. Since on-chip memories are limited, a trigger circuitry is used to only record data related to specific events during the execution. However, during debugging, a circuit recompilation is required on modifying these instruments. This can be very slow, reducing debug productivity. In this article, we propose a non-intrusive and rapid triggering solution with a tailored overlay fabric and mapping algorithm that seeks to enable fast debug iterations without performing a recompilation. This overlay is specialized for small combinational and sequential circuits with a single output; such circuits are typical of common trigger functions. We present an adaptive strategy to construct the overlay fabric using spare FPGA resources at compile time. At debug time, our proposed trigger mapping algorithms adapt to this specialized overlay to rapidly implement combinational and sequential trigger circuits. Our results show that the overlay fabric can be reconfigured to map different triggering scenarios in less than 40s instead of recompiling the circuit during debug iterations, increasing debug productivity.

Programmable logic is emerging as an attractive solution for many digital image processing applications. As image sizes and bit depths grow larger, software has become less useful in the image processing, Field Programmable Gate Array (FPGA) technology has become a viable target for the implementation of algorithms suited to image processing applications, the unique architecture of the FPGA has allowed the technology to be used in many such applications encompassing all aspects of image processing. Image smoothing is one of image processing applications, it often done to reduce the effect of pixel noise in images. This paper presents VHDL architectures (that allow description of the structure design of FPGA) to implement two of image smoothing filters: a) averaging filters b) median filters This research is also applying the filters on FPGA. The results proves high-speed performance of the algorithms that rely on hardware and software compared to software alone, as it appeared very big difference in the speed of execution, depending on the hardware devices that showed the speed of the implementation of the scale of nanosecond, while the software application of algorithms is measured in seconds. The software was implemented in this research using MATLAB 2010 language code as well as the VHDL language to deal with use of FPGA device, which was of a kind (Xilinx XC3S500E Spartan-3E).

Real-time simulation of distribution system is challenging due to its' complex structure consisting of DGs. In this literature, a real-time simulator for distribution system with DG integration based on the field programmable gate array (FPGA) is realized for hardware emulation. The overall framework and asynchronous multi-rate interface method between DG with high nonlinearity and distribution system is proposed. The models of main components in distribution system are designed in FPGA. The hardware parallelism and highly pipeline design is utilized to guarantee real-time simulation, which has strong generality and flexibility. The simulator uses a floating point arithmetic calculation to achieve high accuracy. To validate the new simulator, a photovoltaic-battery hybrid generation system and a typical distribution system integrated with PV generation system are emulated in the hardware. The time-step of DG system and distribution system reach 1.096μs/1.696μs and 2μs/2μs respectively. The captured waveforms show excellent accuracy in comparison to the offline simulation in PSCAD/EMTDC. The time-step is less than RTDS which indicate a higher precision. The resource consumption of FPGA also show advantage compared with RTDS.