Reed-Muller Error-Correction Code Encoder for SFQ-to-CMOS Interface Circuits

This paper presents a study on the merits of single flux quantum (SFQ) logic in superconducting digital electronics. With no requirements for an external RF clock source, the speed of SFQ logic circuits can exceed 100 GHz, orders of magnitude higher than latching logic circuits. Use of overdamped junctions in SFQ circuits makes this logic available for already developed high-Tc junctions. Simulations show the operation of SFQ circuits at above 10 GHz with the junctions having characteristics similar to those of YBa2Cu3O7-x/Au/YBa2Cu3O7-x planar junctions. A similar concept is applied to NbN circuits operable above 10 K. A flip-flop counter using NbN junctions with Vm (1.5 mV)=3 mV and Delta =1.9 mV to model 12 K operation has been successfully simulated up to 5 GHz. Operating margins of only 26% on MVTL shift register were obtained by simulations, which is comparable to the margins for SFQ logic circuits. A counting SFQ analogue-to-digital converter can be improved by using an output buffered quantizer.

Single flux quantum (SFQ) logic families require the development of electronic design automation tools to generate large-scale circuits. The available methodologies or tools for performing timing analysis of SFQ circuits do not have a load-dependent timing characterization method for calculating the context-dependent delay of cells, such as the nonlinear delay model for complementary metal-oxide-semiconductor (CMOS) circuits. A new timing characterization method is presented here for SFQ logic cells, which relies on low-dimensional lookup tables (LUTs) to store the clock-to-output delay, setup, and hold times of clocked cells and input-to-output delay of nonclocked cells in an SFQ standard cell library. Although the delay of Josephson junction based logic cells depends on many parameters, this paper shows that it is possible to reduce this dependency to only a small number of well-chosen parameters. All LUTs are obtained from JSIM simulations for a given target process technology. The accuracy of the proposed LUT-based timing characterization method is compared against JSIM simulations, which shows a maximum error of only 2.1% of the tested clocked cells with different loads.

The decline of Dennard scaling [1] has driven unsustainable power consumption, motivating exploration of post- CMOS technologies. Among these, Josephson Junction (JJ) based Single Flux Quantum (SFQ) logic offers ultrafast switching (tens of GHz) [2], [3] and extremely low switching energy (on the order of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10^{-19}$</tex-math></inline-formula> J) [2], [4]. Even accounting for cooling, SFQ circuits can be up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1000\times$</tex-math></inline-formula> more energy-efficient than CMOS [4], [5], making them an attractive candidate for post-Moore computing. However, SFQ circuit designs are limited by JJ density and thus building SFQ CPUs must be cognizant of this limitation. Due to various SFQ circuit design limitations, such as limited fan out and path balancing, building a SFQ CPU requires spending majority of the JJ budget on control logic. This work proposes Icy-Hot, a novel granular decoupling of the pipeline stages in an SFQ CPU design. Icy-Hot exploits the ultra-fast SFQ computation in the superconducting zone while minimizing the JJ usage for memory and control logic by executing those pipeline stages in existing CMOS technology at 77K. Our evaluation of the proposed design achieves around a 38% power benefit while consuming only about 220,000 JJs.

This paper presents a novel method for accurate margin calculation of single flux quantum (SFQ) logic cells in a superconducting electronic circuit. The proposed method can be utilized as a figure of merit to estimate the robustness of a logic cell without the need for expensive Monte-Carlo simulations. This is achieved through efficient state-space exploration of all parameters in the cell structure. Using the proposed approach, distinct parameter dispersion (DPD) based yield of SFQ cells increases by 55% on average, compared with state-of-the-art techniques.

We have confirmed the importance of the tolerance design for obtaining correct operation in larger-scale Single Flux Quantum (SFQ) logic circuit. Experimental results show that the bias margin of SFQ/dc converter is considerably enhanced by employing tolerance design. The primitives of Single-Flux-Quantum-logic with Ressettable Latch (SFQ-RL) are designed to have high tolerance. As a result, relatively complex circuits based on SFQ-RL including 4-bit Shift Register, 3-Input Majority circuits, binary counter operate correctly with sufficient bias margins. These circuits are fabricated in NEC's standard process using 2.5 kA/cm/sup 2/ Nb/AlOx/Nb junction technology.

We investigated local magnetic flux biasing (LFB) that induces a phase shift in superconductor circuits by locally applying a magnetic field through the superconductor loop with Josephson junctions. The arbitrary phase shift can be achieved using LFB without modifying the circuit fabrication process. To quantitatively evaluate the effects of introducing LFB for practical superconductor circuit applications, we designed a single flux quantum (SFQ) based non-destructive read-out flip-flop with complementary outputs (NDROC) and a delay flip-flop with complementary outputs (DFFC). The circuit area and static power consumption of the NDROC based on LFB architecture (LFB-NDROC) are approximately 67% and 36% of a conventional NDROC, respectively. The measured bias margin of the LFB-NDROC was in the range of 69%–129%. Using LFB, we were able to reduce the circuit area and power consumption for the DFFC by 67% and 83%, respectively. The measured bias margin of the DFFC with LFB was between 115% and 128%. LFB enabled us to implement a 5-to-32 SFQ decoder which comprises NDROC trees with a reduced circuit area of approximately 60% of a conventional decoder. The results obtained in this study can be applied to not just SFQ circuits but other superconductor circuits also, as they improve the area and power efficiency of such circuits.

Living on the verge of the IoT era, the entire world is excited about the potential of mining the monumental amounts of data that would become available in the near future. However, this increasing abundance of data requires supercomputers faster and more powerful than were ever built without the need to build a nuclear plant next to each one! Single flux quantum (SFQ) technology has the potential to meet those booming demands for lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Nevertheless, the promised benefits of three orders of magnitude lower power at an order of magnitude higher performance have yet to be attained. In particular, variability and scalability have been long-term obstacles for the technology to advance, compete, and replace the well-founded Silicon CMOS. Notwithstanding that SFQ fabrication has quite improved over the past two decades, its level of variability has to be taken into design consideration. Moreover, the absence of an established tools flow hinders the scalability and the automatibility, which are among the trumps of CMOS technology in digital VLSI. Specifically, as a consequence, ultra-high-speed clocking of large-scale SFQ circuits in the presence of large levels of variability represents a tough obstacle for the technology to advance. In this paper, we propose an innovative self-adaptive clocking technique, which is designed to be resilient in such uncertain environments. Whereas the traditional balanced tree zero-skew clocking is not reliable for large-scale SFQ designs, our proposed hierarchical chains of homogeneous clover-leaves clocking inherits its robustness from spatially correlated cell delays and from the timing robustness of the SFQ traditional counter-flow clocking. Our simulations on ISCAS'85 benchmark circuits show that our robust clocking costs can be on average within 34% as fast as ideal zero-skew jitter-free clock trees with an average area overhead of 58%. Moreover, lower area overhead is also possible at the cost of performance, demonstrating the possible trade-off between performance and area. We assert that these overheads are acceptable given the benefits of more reliable functionality, as quantified by yield, as well as improved scalability. In particular, previous efforts reported that a similar, but more limited, clocking structure leads to up to 93% higher yield than zero-skew clock trees.

The authors report the design, fabrication, and test results of single flux quantum (SFQ) toggle flip flop circuits. These circuits, investigated as building blocks of an HTS counting ADC, feature a directly coupled readout junction stack similar to those used in LTS RSFQ circuits. The directly coupled circuit delivers higher readout voltage, hence potentially higher operating speed than magnetically coupled alternatives. The circuits were fabricated using two multilayer HTS SNS junction integrated circuit technologies (one at Northrop Grumman and the other at TRW) featuring three YBCO depositions. Initial testing demonstrated toggling of a T-flip flop in response to SFQ pulses generated by integrated dc/SFQ converters. The readout voltage is shown to approach 40% of the junction I/sub C/R/sub N/ product, and as high as 100 /spl mu/V at 65K. Test results are compared with predicted fabrication process parameter requirements. To increase margins and tolerance to process parameter variations, improvements to the design have been made using JSpice and MALT.

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.

In the post-Moore era, slow-growing operating frequency and massive power dissipation make researchers seek new developing directions in integration circuits (ICs). The single flux quantum (SFQ) circuit, a type of superconducting digital circuit, is regarded as an alternative circuit for future computing technology. SFQ circuits are natural gate-level-pipelining synchronous sequential circuits requiring path balancing. However, path balancing may consume enormous resources, as the logic levels of fan-in gates of most gates are different, with the consumption originating from the extra gates (D-Flip-Flops, DFFs) for path balancing and the routing with a much larger clock tree. Hence, in this article, we propose a local optimization method to address the vast consumption problem of the clock tree caused by path balancing in SFQ circuits, primarily relying on self-developed electronic design automation tools for the JSICcomplier for SFQ circuits and using the SIMIT Nb03 cell library. Moreover, we design synchronizer IPs called Dsyn series to replace DFFs in path balancing. The clock nodes and the clocking path consumption are highly reduced by utilizing the proposed strategy, while the new series can be recognized as IPs and easily added to our library, affording scalability. Experiments in a demo S-box circuit demonstrated a percentage of Josephson junctions reduction in clock tree up to 36.48%, while on a few benchmark circuits, the corresponding results are up to 50.69%, demonstrating our method's effectiveness.

As the integration level of superconducting digital circuits increases, flux trapping in these devices becomes a serious problem. High resolution A/D converters and other high speed signal processing systems have been demonstrated with junction counts well into the 10/sup 3/ range. Such large circuits require special testing techniques to prevent flux trapping within the gates, which can reduce bias margins and cause malfunctions of these devices. We discuss the results of experiments using single flux quantum shift registers in which we have varied the ground plane hole pattern and magnetic shield degaussing procedure to minimize flux trapping in these circuits. The operating bias margins of the shift registers have been measured as a function of different testing procedures and ground plane hole designs. In situ degaussing of the magnetic shields aids in the reduction of flux trapping and gave the best results. Measurements of the permeability of mu metal at 4.2 K are discussed.

This E4 section focuses on the preparation of thick and thin films of LTS and HTS materials and describes the base technologies used to develop sophisticated electronic and electrical applications. Low-Tc Josephson junctions are already processed into highly integrated planar structures consisting of 10 stacked Nb layers, with minimum feature size of 250 nm. The circuits include up to about 800,000 single junctions and are intended for low-energy-consumption processors and memories in single flux quantum (SFQ) logics. Other highly promising application directions are currently single photon detectors, superconducting spintronics, and hybrid devices of superconductors and other functional materials. Moreover, the more engineering-related coated conductors are also still a hot topic of research and application.

We review a new approach for digital architectures for software radio. Although direct digitization usually implies the simultaneous digitization of all channels in a particular band at a downconverted IF, we use this term to refer exclusively to the direct digitization of all bands, from near DC to RF. Furthermore, we present results on band selection and digitization of RF signals directly at the carrier frequency with high resolution. These novel approaches are enabled by a superconductor analog-to-digital converter technology using an ultra-fast IC logic known as Rapid Single Flux Quantum (RSFQ) logic, with performance capable of enabling envisioned software radios.

The first single-chip superconductor FLUX-1 microprocessor prototype with a target clock frequency of 17-20 GHz has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using low- temperature 4 kA/cm', 1.75-pm Nb/AlOx/Nb Josephson junction technology. A FLUX-1 chip represents an %bit deeply pipelined microprocessor with a new parallel partitioned architecture that has been developed to tolerate interconnect delays and fill long FLUX-1 pipelines with operations. A FLUX-1 chip contains 65,759 Josephson junctions on a 10.6 mm x 13.2 mm die with flip-chip packaging. First FLUX-I chips fabricated in 2001 are currently under testing at TRW.

Influence of initial counter-layer deposition condition using double-plume PLD method on characteristics of interface-modified Josephson junctions