Reliability Analysis of Operating Systems and Software Stack for Embedded Systems

Graphics processing units (GPUs) are the reference architecture to accelerate high-performance computing applications and the training/interference of convolutional neural networks. For both these domains, performance and reliability are two of the main constraints. It is believed that the only way to increase reliability is to sacrifice performance, e.g., using redundancies. We show in this paper that this is not always the case. As a very promising result, we found that most GPUs performance improvements also bring the benefit of increasing the number of executions correctly completed before experiencing a silent data corruption (SDC). We consider four different common GPUs’ performance optimizations: architectural solutions, software implementations, compiler optimizations, and threads degree of parallelism. We compare different implementations of a variety of parallel codes and, through beam experiments and applications profiling, we show that the performance improvement typically (but not necessarily) increases the GPU SDC rate. Nevertheless, for the vast majority of the configurations the performance gain is much higher than the SDC rate increase, allowing to process a higher amount of correct data. As we show, the programmer choices can increase up to 25×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$25\ imes {}$$\\end{document} the number of correctly completed executions without redesigning the algorithm nor including specific hardening solutions.

Time driven real-time systems are of increasing importance in the field of critical computer control applications [Sta90]. Because of their predictable behavior they are well suited for systems whose correct operation in the time domain must be guaranteed already in the design phase of an application. Time driven systems allow the proof of the correct timing behavior of an application by construction of a feasible schedule.In the MARS system [Kop89] the time driven approach is realized. The structure of the MARS operating system kernel differs significantly from that of others because of the specific demands which a distributed time driven system imposes on its underlying operating system. Based on the experiences with the first prototype of the MARS operating system [Dam89] (MARS-1), a new operating system kernel, MARS-2, has been developed from scratch. There have been some motivations for the development of MARS-2:• New processor boards ('MARS components') have been developed to fully support the MARS concepts [Ste91]. These boards provide mechanisms to achieve a high self-checking coverage and a highly predictable timing behavior.• The introduction of new concepts and mechanisms into the MARS system (e.g. membership protocol, time redundant process execution, shadow component [Kop90], [Kop91]) requires support by the runtime system.• A predictable timing behavior should be achieved by the new kernel. Although the system overhead caused by the old implementation was boundable in principle, the calculated bounds were too high to guarantee the correct timing behavior of an application already at design time [Vrc91].• The self-checking coverage of the MARS components has to be high because the fault tolerance mechanisms of MARS are based on it. Whereas the old kernel was not specifically designed in order to meet this requirement, MARS-2 uses both hardware and software mechanisms to increase the self-checking coverage to a sufficiently high degree.MARS-2 is based on a microkernel operating system architecture in contrast to the monolithic kernel of MARS-1.

The underlying operating system of transparent computing system TcOS is booting slowly and is taking up too much memory space. To solve these problems, this paper proposes a method of optimizing the kernel and application layer. It includes recompiling the kernel, modifying the kernel configuration, simplifying services and gnome desktop of the operating system. Experimental results show that the time of booting the optimized operating system is decreased by 33.11% and the memory space usage is 40.43% less than before.

Mobile computational offloading offers a solution to extend the computational power of a mobile device allowing it to run heavyweight activities/tasks. This turns low-end mobile devices into a capable machine of running heavyweight applications that require special processing power. Code offloading is achieved through migration. Migrating code from a local machine (i.e. mobile device) to the cloud where the code is actually executed is challenging. Questions such as when and how migration takes place are critical. Quite a few offloading frameworks are proposed in the literature. They are, mostly, mostly not efficient due to the lack of a standard offloading architecture, some did not propose an architecture at all. The abundance of Quality of Service (QoS) component is another concern. This paper introduces a layered approach to mobile computation offloading called LAMCO. LAMCO is implemented in the Android operating system and the run-time performance of the framework is evaluated in this paper. One advantage of LAMCO is that it does not require any modifications in the underlying operating system as the framework is dynamically installed and updated while the operating system is intact.

The reliability of cyber forensic evidence acquisition is strongly influenced by the underlying operating systems, Windows, macOS, and Linux - due to inherent variations in file system structures, encryption protocols, and forensic tool compatibility. Disk forensics, one of the most widely used techniques in digital investigations, faces distinct obstacles on each platform. Windows, with its predominantly NTFS and FAT file systems, typically supports reliable disk imaging and analysis through established tools such as FTK Imager and Autopsy/Sleuth Kit. However, encryption features frequently pose challenges to evidence acquisition. Conversely, Linux environments, which rely on file systems like ext4 and XFS, generally offer greater transparency, yet the transient nature of log retention often complicates forensic analysis. In instances where anti-forensic strategies—such as encryption and compression— render traditional disk forensics insufficient, memory forensics becomes crucial. While memory forensic methodologies demonstrate robustness across Windows and Linux platforms forms through frameworks like Volatility, platform-specific difficulties persist. Memory analysis on Linux systems benefits from tools like LiME, snapshot utilities, and dd for memory acquisition; nevertheless, live memory acquisition on Linux can still present challenges. This research systematically assesses both disk and memory forensic acquisition techniques across samples representing Windows and Linux systems. By identifying effective combinations of forensic tools and configurations tailored to each operating system, the study aims to improve the accuracy and reliability of evidence collection. It further evaluates current forensic tools and highlights a persistent gap: consistently assuring forensic input reliability and footprint integrity. By integrating static analysis with temporal performance evaluations, this study emphasizes the importance of developing standardized forensic procedures to ensure the integrity and admissibility of evidence across diverse platforms. Establishing such standardized methodologies is imperative to maintaining the credibility and reliability of cyber forensic investigations in heterogeneous operating system environments.

Reliability and safety analysis for systems of fusion device

This paper discuss on how to develop a hard real-time machine control system with Microsoft Windows NT Operating System, where the respond must be within 0.5 milliseconds. The attempt to use a general-purpose operating system (Microsoft Windows NT 4.0 Workstation) is because there is abundance of Commercial-Off-the-Shelf Components (COTS), easily available tools (compilers, and 3 party tools) and need not to learn another operating system behavior. The most important factor is there is no single dominant operating system or tools vendor for real-time operating system. Since the no single dominant real-time operating system development under real-time operating system is riskier and more costly. Ideally codes must be portable between different operating system where it is apparent with Windows platforms, Windows 95/98, Windows ME, Windows 2000, Windows XP or even Windows CE. Firstly study was done on how Microsoft Windows NT operating system works internally from materials from Microsoft Software Development Network (MSDN). Secondly study was done how to take advantage of the operating system to create a real time application. Microsoft Windows NT is a general purpose operating system that does not support real time application development, but it has all the vital elements that a real time operating system needs. The vital elements are priority-driven, preemptive scheduler, preemptive interrupt handler (for critical interrupts), deferred procedure calls (DPC) for non-critical (DPC executes after ISR), synchronization and deterministic response time. With these vital elements and some modification to application codes to enable it to execute in higher priority level, would result a real time application. This does not mean changing all the codes to higher priority is the solution, as it would cause system to malfunction as other device driver or low-level interface run at high priority too and this would lock up the system. With the combination of priority level, synchronization a complete real time solution can be implemented and this paper covers the concept. This concept also explains what was done to overcome the need of special hardware (as recommended) to accomplish hard real-time application with the response of 0.5 milliseconds.

Realizing integrated prioritized service in the Hadoop cloud system

Blockchain: The operating system of smart cities

Virtualization is becoming a prominent field of research not only in distributed systems, but also in software protection and obfuscation. Software virtualization has given rise to advanced techniques that may provide intellectual property protection and anti-cloning resilience. We present results of an empirical study that answers whether integrity of execution can be preserved for process-level virtualization protection schemes in the face of adversarial analysis. Our particular approach considers exploits that target the virtual execution environment itself and how it interacts with the underlying host operating system and hardware. We give initial results that indicate such protection mechanisms may be vulnerable at the level where the virtualized code interacts with the underlying operating system. The resolution of whether such attacks can undermine security will help create better detection and analysis methods for malware that also employ software virtualization. Our findings help frame research for additional mitigation techniques using hardware-based integration or hybrid virtualization techniques that can better defend legitimate uses of virtualized software protection.

: Over the past few years, virtualization has been employed to environments ranging from densely populated cloud computing clusters to home desktop computers. Security researchers embraced virtual machine monitors (VMMs) as a new mechanism to guarantee deep isolation of untrusted software components. Unfortunately, their widespread adoption promoted VMMs as a prime target for attackers. In this paper, we present HyperCheck, a hardware-assisted tampering detection framework designed to protect the integrity of VMMs and, for some classes of attacks, the underlying operating system (OS). HyperCheck leverages the CPU System Management Mode (SMM), present in x86 systems, to securely generate and transmit the full state of the protected machine to an external server. Using HyperCheck, we were able to ferret-out rootkits that targeted the integrity of both the Xen hypervisor and traditional OSes. Moreover, HyperCheck is robust against attacks that aim to disable or block its operation. Our experimental results show that HyperCheck can produce and communicate a scan of the state of the protected software in less than 40ms.

This paper compares the performance of operational short-range ocean forecast systems developed under the Global Ocean Data Assimilation Experiment (GODAE) – an international effort to demonstrate the feasibility of operational ocean forecasting. ‘Best estimates’ from four different operational forecast systems (either analyses, hindcasts, or nowcasts) are inter-compared for the Tasman and Coral Seas, off eastern Australia. Systems considered include those developed in Australia, France, the USA, and the UK. Each system is compared to observations of along-track sea-level anomaly, sea-surface temperature, near-surface velocity, and sub-surface temperature and salinity. All have their strengths and weaknesses, and each system out-performs all others in one aspect or another. With few exceptions, all systems demonstrate signal-to-noise ratios greater than one for all variables. Due to the Australian focus, in addition to the best estimates from the operational systems, operational forecasts and a delayed-mode reanalysis are also inter-compared using the Australian system. The Australian system generally performs the best for sea-level anomaly; the French system is best for near-surface velocities; the USA system generally performs the best for sea-surface temperature; and the UK system is best for sub-surface temperature and salinity. These findings provide useful indicators of deficiencies in each system and clear metrics by which future developments should be assessed. Based on these results and other practical considerations the adoption of multimodel consensus forecasting, using all available forecasts from all systems, is promoted as the most robust approach for the user community. Such developments are being pursued under GODAE OceanView – the successor to GODAE. The results show the success of GODAE in demonstrating the feasibility of operational oceanography.

Many practical systems are phased-mission systems (PMSs), where the mission consists of multiple, consecutive, and non-overlapping phases of operation. An accurate reliability analysis of a PMS must consider statistical dependence of component states across phases, as well as dynamics in system configurations, success criteria, and component behavior. This paper proposes a new method based on multiple-valued decision diagrams (MDDs) for the reliability analysis of a non-repairable binary-state PMS. Due to its multi-valued logic nature, the MDD model has recently been applied to the reliability analysis of multistate systems. In this work, we present a novel way to adapt MDDs for the reliability analysis of systems with multiple phases. Examples show how the MDD models are generated and evaluated to obtain the mission reliability measures. Performance of the MDD-based method is compared with an existing binary decision diagram (BDD)-based method for PMS analysis. Empirical results show that the MDD-based method can offer lower computational complexity as well as a simpler model construction and improved evaluation algorithms over those used in the BDD-based method.

Large Language Models (LLMs) are being increasingly applied in various natural language processing tasks including safety-critical systems (e.g., medical diagnosis querying, and code generation for self-driving), where resilience to hardware transient faults is essential for guaranteed safety. Traditional Fault Injection (FI) approaches are time consuming due to a large number of repeated executions, which limits their scalability to fast evaluate large-scale resilience. To address these challenges, we propose LLM-IARE, a novel Input-Aware Resilience Estimation Model for LLMs under hardware transient faults. It takes advantage of twice static analysis and once dynamic execution to extract critical parameters to compute general resilience metrics such as Silent Data Corruption (SDC) rates. Fast static analysis can obtain the primary LLM parameters, while dynamic execution can provide input-sensitive attention profiling to characterize how input variations influence internal attention patterns dynamically. More importantly, our proposed LLM-IARE uses the obtained parameters for modeling at three levels (operation, module, and layer) so that the SDC rates of transient fault impacts on LLMs can be calculated quickly and accurately. Additionally, LLM-IARE is further extended to estimate the LLM application-level resilience metric, the cosine similarity reflecting the bit-upset induced semantic fault impacts on final output quality. Comprehensive experiments on six representative LLMs (for example, GPT-2, T5 and RoBERTa), and 30 BERT variants demonstrate that LLM-IARE achieves a fast and accurate LLMs resilience evaluation, with up to 7335 × (average 4500 ×) speedup and an average logarithmic relative error of 3.94% compared to advanced LLVM-based fault injection methods. We further extend the evaluation to four larger Qwen2.5 models (0.5B–7B), where LLM-IARE maintains stable accuracy with logarithmic relative errors between 1.96% and 4.21% (average 3.39%).

Reconfigurable supercomputers are a possible next generation architecture for traditional cluster-based supercomputers. In this cluster-based architecture, coprocessor boards will be added to each node for application-specific acceleration. There are many interesting coprocessor boards with Field-Programmable Gate Arrays (FPGAs) that are well matched with supercomputing codes. Already large-scale supercomputing clusters have been plagued by memory upsets due to neutron-based terrestrial radiation, which is a situation bound to worsen with the addition of co-processor boards. These memory upsets can cause silent data corruption and unreproducible system crashes. FPGAbased reconfigurable supercomputers will also be susceptible to circuit changes from memory upsets. Therefore, reliability analysis of these systems and their codes is a necessary step in designing and using these machines. In this abstract, we present an overview of a reliability analysis toolset, called the Scalable Tool for the Analysis of Reliable Systems (STAR Systems), with modules for determining the reliability of FPGA designs (STAR-Circuits) and reconfigurable supercomputers (STAR-Reconfigurable SuperComputers).