Remarks on simulation of Boolean functions

Execution of all-optical Boolean OR logic using carrier reservoir semiconductor optical amplifier-assisted delayed interferometer

Conventional processors often underutilize their computational resources because of the fixed functionality of logic gates; numerous logic gates should be embedded to support all necessary operations, even if many of them are rarely used. Reconfigurable logic gates (RLGs) offer a promising solution as they dynamically switch their logical functionality according to the demands of specific operations. Here, a novel RLG architecture based on the dual‐gate silicon nanomembrane (SiNM) field‐effect transistors (FETs) is proposed. By reconfiguring the electrostatic doping profiles of the SiNM channel, the dual‐gate SiNM FET can operate as three distinct electronic components; a forward‐biased diode, a backward‐biased diode, and a variable resistor. Furthermore, the three dual‐gate SiNM FETs are integrated to implement a single RLG, whose Boolean logic functions can be reconfigured between AND and OR operations. In addition, an array of three RLGs can be used to perform 32‐bit masking operations, thereby validating their effectiveness in digital data processing.

The rapid advancement of Artificial Intelligence Generated Content (AIGC) technologies challenges fake speech detection with an ever-evolving diversity of spoofed audio. Current approaches, which rely on a classification-based perspective, are highly dependent on a big amount of training data and show limited generalization to unseen attack types. To address these limitations, this paper introduces a brain-inspired, multi-clue detection paradigm. We propose a perception-decision machine composed of two core components. The perception module utilizes multiple independent detectors, each optimized for Maximum Detection Precision (MaxDP) to identify a specific forgery clue. By standardizing their outputs into binary Boolean values, this design allows for flexible computational models. The decision-making module then renders a final judgment by first evaluating learned combinations of the detected clues through a logical reasoning process. The outcomes of this reasoning are then aggregated using a variable-length OR operation, a mechanism that enables the seamless incremental learning of new forgery clues without retraining the entire system. Our results validate the effectiveness of the multi-clue detection perspective, demonstrating the framework's potential for enhanced explainability and practical adaptability to new threats.

An analysis of operation and selection of reliability indicators for specialized computers (SEVMs) of aerospace equipment was carried out. The requirements for the methods of redundant computer systems are formulated. A comparative evaluation of the detecting ability and hardware costs in the implementation of the majority method of redundancy, the method of duplication and the use of corrective codes is carried out. The expediency of using the duplication method to increase the probability of failure-free operation and survivability of self-healing digital computers, using algebraic linear codes, to identify a faulty backup channel is substantiated. Unlike the known codes, it is proposed to use an algebraic linear code, in which the values of the check bits correspond to the direct and inverse values of the information bits, which makes it possible to detect errors when reading information from the inverse outputs of the memory, correct single errors, detect double errors and control the logical operation of inverting required to represent a negative number in an additional code, which makes it possible to adapt the code to control the arithmetic and logical operations of the computer processor. The evaluation of the probability of failure-free operation of a duplicated computer, with its general redundancy, with the detection and correction of single errors in the backup memory channels and the detection of errors in the backup channels of the processor ALU based on the proposed code, and the assessment of the probability of failure-free operation of the computer, with its separate redundancy, with error detection in the backup channels of the duplicated memory based on the Hamming code and error correction in the backup channels of the processor ALU based on the majority method. As a result of comparing the probabilities of failure-free operation, it has been established that the total reservation of the computer based on the proposed code, in comparison with the separate reservation of the memory and ALU of the processor of the computer, makes it possible to provide a gain in the probability of failure-free operation of the computer and its functional units throughout the entire period of operation.

A central challenge in sensory neuroscience involves understanding how neural circuits shape computations across cascaded cell layers. Here we attempt to reconstruct the response properties of experimentally unobserved neurons in the interior of a multilayered neural circuit, using cascaded linear-nonlinear (LN-LN) models. We combine non-smooth regularization with proximal consensus algorithms to overcome difficulties in fitting such models that arise from the high dimensionality of their parameter space. We apply this framework to retinal ganglion cell processing, learning LN-LN models of retinal circuitry consisting of thousands of parameters, using 40 minutes of responses to white noise. Our models demonstrate a 53% improvement in predicting ganglion cell spikes over classical linear-nonlinear (LN) models. Internal nonlinear subunits of the model match properties of retinal bipolar cells in both receptive field structure and number. Subunits have consistently high thresholds, supressing all but a small fraction of inputs, leading to sparse activity patterns in which only one subunit drives ganglion cell spiking at any time. From the model’s parameters, we predict that the removal of visual redundancies through stimulus decorrelation across space, a central tenet of efficient coding theory, originates primarily from bipolar cell synapses. Furthermore, the composite nonlinear computation performed by retinal circuitry corresponds to a boolean OR function applied to bipolar cell feature detectors. Our methods are statistically and computationally efficient, enabling us to rapidly learn hierarchical non-linear models as well as efficiently compute widely used descriptive statistics such as the spike triggered average (STA) and covariance (STC) for high dimensional stimuli. This general computational framework may aid in extracting principles of nonlinear hierarchical sensory processing across diverse modalities from limited data.

Optics has already proved its strong potentiality for conducting parallel logic, arithmetic and algebraic operations. Since last few decades so many all-optical data processors were proposed. To implement these processors different encoding / decoding techniques, such as polarization encoding, intensity encoding, phase encoding technique have been reported. Very recently ‘frequency encoding’ technique have drawn a special interest to the scientific community. The frequency is the fundamental character of a signal and it preserves its identity irrespective of reflection, refraction, transmission, absorption throughout the communication. Therefore, if two specific frequencies are encoded as 1 state and 0 states respectively, then one can ensure about the state of information throughout the communications. In this paper the authors propose a method of conducting inversion OR, NOR and NAND logic operations exploiting the wavelength conversion, which is achieved by exploiting the cross gain modulation (XGM) property of reflecting semiconductor optical amplifier (RSOA), as well as the property of change of nonlinear rotation of the state of polarization of probe beam by cross phase modulation (XPM). Both the wavelength conversion properties are controlled by the intensity of the pump beam. The major advantage of SOA-switching over any other conventional switching is that SOA-switching require low power with good on off contrast ratio. Again as the NAND and NOR are the universal logic gates, so any other logic operation can be implemented using this concept.

A Generalization of the Noisy-Or Model

Probabilistic computing, with its efficient and non‐deterministic computational model, holds great potential and is driving a paradigm shift in computation. However, traditional CMOS circuits face issues such as a high device count, significant energy consumption, and pseudo‐random behavior. Additionally, commonly used probabilistic computing devices like LBNM and sMTJ suffer from problems related to volatility and initialization. This paper explores the application of non‐volatile combined bit (c‐bit) devices, exhibiting back‐hopping‐like phenomena, in logical operations, arithmetic computations, and data backup and recovery. Logical reverse inferences are successfully implemented for AND, OR, XOR, and XNOR operations. Importantly, the logical reverse inference of full and half adders is achieved, as well as the decomposition of addends, verifying the feasibility of c‐bit devices in complex arithmetic operations. Furthermore, by utilizing multiple c‐bit devices working in tandem, efficient data backup and reliable recovery are achieved, offering a novel solution for data security. This research not only enriches the theoretical framework of probabilistic computing but also provides new insights and directions for the future development of computational models.

Satisfiability Modulo Theories (SMT) refers to the problem of deciding the satisfiability of a formula with respect to certain background first-order theories. In this article, we focus on Satisfiablity Modulo Integer Arithmetic, which is referred to as SMT(IA), including both linear and non-linear integer arithmetic theories. Dominant approaches to SMT rely on calling a CDCL-based SAT solver, either in a lazy or eager flavour. Local search, a competitive approach to solving combinatorial problems including SAT, however, has not been well studied for SMT. We develop the first local-search algorithm for SMT(IA) by directly operating on variables, breaking through the traditional framework. We propose a local-search framework by considering the distinctions between Boolean and integer variables. Moreover, we design a novel operator and scoring functions tailored for integer arithmetic, as well as a two-level operation selection heuristic. Putting these together, we develop a local search SMT(IA) solver called LocalSMT. Experiments are carried out to evaluate LocalSMT on benchmark sets from SMT-LIB. The results show that LocalSMT is competitive and complementary with state-of-the-art SMT solvers, and performs particularly well on those formulae with only integer variables. A simple sequential portfolio with Z3 improves the state-of-the-art on satisfiable benchmark sets from SMT-LIB.

Multiplication is commonly used arithmetic operation in computers. An algorithm is proposed to perform multiplication of positive numbers using law of indices. The two inputs A and B are represented as binary numbers. Iteratively, the number A is multiplied with the bits in B. The coefficients of the partial products are accumulated. These coefficients are represented as binary numbers, the result coefficients are calculated. The proposed algorithm is simulated using Quartus 2 tool for two four bit inputs. An improvement in timing by 18% with comparable power consumption and increased area is observed for input of four bits. The proposed algorithm can be extended for n-bit inputs.

A novel approach to arithmetic operations in digital computers is described which combines digital and analog techniques. This is accomplished by using parallel-serial interconnections of digital/analog converters. The interconnections are under stored program control and are effected by selecting multiplexers which route the analog signals to perform various arithmetic operations. The final analog signal, which is the result of the computation is converted to digital form by means of an analog/digital converter.Because of the extreme parallel nature of D/A Arithmetic, high computational speeds are attained, although all the circuitry is operating slowly by present digital computer standards. Using present techniques the analog nature of the computation limits the accuracy to four or five significant decimal figures. Therefore, the D/A Arithmetic Unit could not replace the arithmetic unit presently in digital computers, but could be used to solve problems or parts of problems that do not require extreme accuracy.

Arithmetic Operations in Quantum-DNA Computing

The analog AC-voltmeter usually can only measure the ideal-sinusoid voltage with narrow frequency range. Meanwhile, in fact the grid voltage is often not in the form of an ideal sinusoidal. To be able to measure a non-sinusoidal AC voltage with a wide range of frequency, a true-RMS voltmeter is needed. The research designed a true RMS measuring system using an ATmega 328P microcontroller. The input voltage is converted to pulse using Schmit triger and fed to the microcontroller’s external interrupt pin to calculate the input signal frequency. Meanwhile the microcontroller’s ADC sampled the input signal with a frequency of 128 times the signal’s frequency. RMS voltage calculations are performed using arithmetic operations for 16 and 32 bit integer variables. The test results show that the system can measure voltages with zero errors from 100 to 275 volts with a frequency of 50 Hz. The system can also measure voltages with zero errors at 220 volt with frequencies from 40 Hz to 150 Hz. However, this system can still be used to measure voltages ranging from 25 volts to 300 volts at frequencies from 35 Hz to 195 Hz with an average error of 0.21%. During RMS voltage calculation, the microcontroller’s CPU usage was 13.35%, so that this system can be further developed.

Chapter 7 - Arithmetic Operations

Data mining acquires knowledge and rules that is connotative, unknown and having potential value for decision-making from large databases or data warehouses. Existing association rule mining algorithms and modules cater to a centralized environment, such as database or data warehouse. With the development of distributed database and network technology, they don't meet the needs of mining rules from distributed data sets. In this paper, we provide a mining model based on the distributed database and a corresponding effective mining algorithm. Using association rules of market basket analysis, integrate every database file, then get the mining result, and make a further mining upon the mining method, transport the rules which are not fit with the requirements back to each distributed station to make a more accurate mining process, thus avoiding the frequent network communication. This algorithm can reduce frequent communication burden, they has an distinguish virtue in parallel arithmetic computing and asynchronous operation & heterogeneous mining.