Report on workshop on operating systems support for next generation large scale NVRAM (NVRAMOS 2009)

Phase change memory (PCM) is known for its potentials as main memory and as storage. In contrast to the past work, this work presents a PCM translation layer that considers how the main memory is used by the operating system together with the usage patterns of storage by trading their performance and reliability. In particular, a joint management scheme is proposed to improve the capability of PCM as both main memory and storage so as to enhance the performance of the entire system. The endurance issue of PCM for main memory is resolved by utilizing the potentially large capacity of the PCM storage space with limited modifications to the existing operating system implementations. Moreover, three commands are proposed to help operating system engineers to take advantage of PCM as main memory and storage by reducing I/O overheads and speeding up both the initialization and termination of program executions. The experimental results show that the performance of PCM as both main memory and storage can be significantly improved with reasonable lifetime, while the system overhead is very limited under coarse-grained wear leveling.

Aim. To identify the connection between visual and sound perception. Methodology. Using Object-Oriented Programming (OOP) of the Python language, we are looking for a way to convert a visual (pixel) display into an audio display. A number of modern and functional libraries are used. Modern methods of “packing” all software components into a single file are used for convenient program deployment on an electronic computing device (computer) with any modern operating system (OS). Results. A software product based on the modern object-oriented programming language and functional libraries was created, which allows to present the pixel structure of a visual image in a sound display format.Research implications. The significance lies in the disclosure of a modern way of “packing” all software components into a single file for convenient program deployment on an electronic computing device (computer) with any modern operating system (OS).

The programming of the interrupt handling mechanisms, process switching primitives, scheduling mechanisms, and synchronization primitives of an operating system for a multiprocessor require both efficient code in order to support the needs of high-performance or real-time applications and careful organization to facilitate maintenance. Although many advantages have been claimed for object-oriented class hierarchical languages and their corresponding design methodologies, the application of these techniques to the design of the primitives within an operating system has not been widely demonstrated.To investigate the role of class hierarchical design in systems programming, the authors have constructed the Choices multiprocessor operating system architecture using the C++ programming language. During the implementation, it was found that many operating system design concerns can be represented advantageously using a class hierarchical approach, including: the separation of mechanism and policy; the organization of an operating system into layers, each of which represents an abstract machine; and the notions of process and exception management. In this paper, we discuss an implementation of the low-level primitives of this system and outline the strategy by which we developed our solution.

Virtual memory was developed to automate the movement of program code and data between main memory and secondary storage to give the appearance of a single. This technique greatly simplified the programmer’s job, particularly when program code and data exceeded the main memory’s size. In modern operating system, secure file system can protect confidential data from unauthorized access. However, once an authorized process has accessed data from a cryptographic file system, the data can appear as plaintext in the unprotected virtual memory backing store, even after system shutdown. This paper proposes new approach for adding multilevel security capability to virtual memory management. It uses partial swap encryption based on process’s security policy. Volatile encryption keys are chosen randomly, and remain valid only for short time periods. Performance comparison shows the total overhead of proposed method.

Operating systems is the last required course in our undergraduate Computer Science major. Although our students have had two semesters of programming in C++, one in assembler, and a semester of data structures using the C++ Standard Template Library, many of them have weak mastery of some important programming topics. In addition, they have had minimal exposure to using these constructs with real world data structures. In this paper we describe how we have used the assignments in a Linux-based Operating Systems course to remedy these deficiencies while teaching a full semester of OS content. Assignments include retrieving data via standard API calls and from /proc; process management, including fork, wait and system; building a microshell with fork/exec and pipe/dup; semaphore handling; and building an OS simulator. We have rewritten these assignments to provide additional practice with data type conversion, pointers and memory management, file handling, classes and subclasses, and the use of vectors, maps and other data structures in the STL.

Monolithic operating systems: (1) are centralized, (2) need additional effort for distributed computing, (3) cannot deal with the speed of adaptation necessary for modern heterogeneous infrastructures, (4) require more resources than available on embedded devices. Modern Operating Systems need to reflect the application structure better, in the sense that they have to reduce the impact on the environment by focusing only on what is needed locally, rather than trying to cater for all potential cases. Modular Operating Systems offer dedicated “modules” for local execution of distributed and scalable applications with minimal overhead and maximum integration across instances. Inclusion of heterogeneous infrastructures requires only the adaptation of individual modules, rather than the whole operating system. This chapter discusses the architecture, usability and constraints of modular operating systems for large scale, distributed and heterogeneous environments.

Virtual memory techniques are available in modern operating system will permits the execution of a program even if it is partially available in memory thus providing an illusion of very large memory to the user and freeing the user from the concern of large program size. The primary storage size has increased by multiple order of magnitude. With several gigabytes of primary memory, algorithms that require a periodic check of each and every memory frame are becoming less and least practical. Some basic assumptions used by the traditional page replacement algorithms were invalidated, resulting in a revival of research area. Currently the usage of the object oriented programming is much higher than the structured programming. Hence the locality of reference of user software has weakened. Due to the above problem for the page replacement methods also we have to think about new methods. In this paper mainly focused on the improvement of the processor performance. In order to achieve this, the number of page faults are tried to reduce, by using the page replacement method in the correct way. In modern operating systems mainly make use of the Least Recently Used (LRU) page replacement method, in which only the arrival time of the pages to the page frame are make used. Here we made an attempt to consider both the arrival time and the number of reference done on the page is considered. By consider these two parameter we developed a new algorithm Least Recently Used and Least Frequently Used (LRU-LFU) which will give a better performance than LRU page replacement method.

In the near future new technologies will make it possible to enlarge the main memory layer in the current memory hierarchy using devices with small cost and access penalties, such as the Storage Class Memory (SCM). In order to use those technologies as efficiently as possible, we need to understand how the developer and the operating system can get the best performances while managing a new heterogeneous main memory, which consists of multiple types of memory with different volumes and different access speeds. We found that the most reasonable way to introduce these new technologies into any usable memory system would be by using a new automated layer that selects the most appropriate memory levels for allocating space in the memory complex, and that moves data between memory levels of the memory complex for optimizing performance in the fashion of paging algorithms. Specifically, we discovered that this memory management is optimized using a modification of the Aging algorithm (a directive of the LRU concept) -- a modification which can improve the access speed of the heterogeneous main memory by about 75%, and that manages to achieve the same or better Hit / Miss ratio in almost all cases in comparison to the current alternatives.

In this paper we focus on the design and implementation of low cost, cross language and cross platform Information Retrieval and Documentation tools capable for the collection, organization and administration of unstructured and semi-structured information imported from various sources. A modular Computer Assisted Information Resources Navigation (CAIRN) software architecture is proposed and the requirements of each module are presented. A discussion of the implementation is based on the experimentation with a prototype of such a software tool. The technologies that are incorporated into the modern operating systems and the opportunities that they offer for implementing the modules of the CAIRN architecture are also examined and evaluated. Some of these technologies are common / independent from the operating systems, while some others are distinctive. In this latter case we face barriers (restrictions) for a straightforward implementation of the CAIRN software systems to the whole range of desktop operating systems (e.g. Windows, Mac OS, Linux, Solaris). Some alternative technologies are presented to avoid this serious constraint. The evaluation of the implementation effort is also discussed and eventually some conclusions and future plans for further improvement of the CAIRN architecture are given.

This study explores AI-optimized scheduling and resource management in modern operating systems, addressing challenges related to efficiency, adaptability, and energy consumption.Traditional scheduling techniques struggle to handle dynamic workloads effectively, whereas AI-driven approaches, such as reinforcement learning and neural architecture search, enable real-time workload prediction and optimized task execution.These methods enhance CPU utilization, reduce latency, and improve power efficiency, making them well-suited for cloud computing, multi-core processing, and mobile environments.Despite challenges such as computational overhead and security risks, ongoing advancements in AI continue to refine scheduling strategies, paving the way for more adaptive and efficient next-generation operating systems.

In many modern operating systems (OSs), there exists no isolation between different kernel components, i.e., the failure of one component can affect the whole kernel. While microkernel OSs introduce address space separation for large parts of the OS, their improved fault isolation comes at the cost of performance. Despite significant improvements in modern microkernels, monolithic OSs like Linux are still prevalent in many systems. To achieve fault isolation in addition to high performance and code reuse in these systems, approaches to move only fractions of kernel code into user mode have been proposed. These approaches solely rely on static code analyses for deciding which code to isolate, neglecting dynamic properties like invocation frequencies. We propose to augment static code analyses with runtime data to achieve better estimates of dynamic properties for common case operation. We assess the impact of runtime data on the decision what code to isolate and the impact of that decision on the performance of such “microkernelized” systems. We extend an existing tool chain to implement automated code partitioning for existing monolithic kernel code and validate our approach in a case study of two widely used Linux device drivers and a file system.

Byte addressable non-volatile (NV) memory, such as STT-RAM, MRAM, and PCM, is the next generation memory that can be used as both main memory and secondary storage. While it can persistently store data without power supply, its access speed is comparable to DRAM. While there have been the active researches on its use for either main memory or secondary storage, these researches were conducted independently. This paper presents the integration methods of the main memory and file system management for NV memory, so that it can be used as both main memory and storage. The presented methods use a file system as their basis for the NV memory management; thus, the internal data structures of a file system can have impacts upon the performance of the integration methods. We implemented the proposed methods in the Linux kernel, and performed the evaluation on a system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory.

The wireless sensor network (WSN) is an interesting area for modern day research groups. Tiny sensor nodes are deployed in a diversity of environments but with limited resources. Scarce resources compel researchers to employ an operating system that requires limited memory and minimum power. Tiny operating system (TinyOS) is a widely used operating system for sensor nodes, which provides concurrency and flexibility while adhering to the constraints of scarce resources. Comparatively, TinyOS is considered to be the most robust, innovative, energy-efficient, and widely used operating system in sensor networks. This paper looks at the state-of-the-art TinyOS and the different dimensions of its design paradigm, programming model, execution model, scheduling algorithms, concurrency, memory management, hardware support platforms, and other features. The addition of different features in TinyOS makes it the operating system of choice for WSNs. Sensing nodes with TinyOS seem to show more flexibility in supporting diverse types of sensing applications.

The broad spectrum of universities, industrial research laboratories, and computer companies represented at the Second IEEE Workshop on Workstation Operating Systems provided a rich snapshot of current activities in operating systems. There were representatives of 19 operating system research projects among the participants and several from commercial offerings. The attendees came from seven countries on three continents: North America, Europe, and South America.Since the last Workshop in 1987, there have been more advances in hardware than in software functions. Software standards continue to emerge in the areas of operating system interfaces, page description languages, window management interfaces, and communication protocols. New software applications exist in the areas of multimedia and multi-node computing. Object-oriented technology is already present in running systems and gaining importance. The areas that the participants perceived needing most future work were operating system abstractions, workstation operation, system responsiveness, input output, network services, management of clusters of workstations, and failure handling.While processor speeds, main memory access speeds, memory density, and secondary storage capacity continue to increase fast, disk seek times have decreased only slightly, and the bandwidth of most local-area networks has not increased at all. FDDI networks are just beginning to be deployed. The software is adjusting to this hardware scenario by using caching at multiple levels of the systems.In the last two years large main memories at individual computing nodes and multi-node computer installations have become common. It is expected that most future computing nodes will have substantial local storage and that high-bandwidth networks will enable the support of continuous media like vocie and video. Input output, to disks, to networks, and to user-oriented devices, is expected to become the central problem in future systems.

In the big data era, a huge number of services has placed a fast-growing demand on the capacity of DRAM-based main memory. However, due to the high hardware cost and serious leakage power/energy consumption, the growth rate of DRAM capacity cannot meet the increased rate of the required main memory space when the energy or hardware cost is a critical concern. To tackle this issue, hybrid main-memory devices/modules have been proposed to replace the pure DRAM main memory with a hybrid main memory module that provides a large main memory space by integrating a small-sized DRAM and a large-sized non-volatile memory (NVM) into the same memory module. Although NVMs have high-density and low-cost features, they suffer from the low read/write performance and low endurance issue, compared to DRAM. Thus, inside the hybrid main-memory module, it also includes a memory management design to use DRAM as the cache of NVMs to enhance its performance and lifetime. However, it also introduces new design challenges in both the OS and the memory module. In this work, we rethink the interactivity of OS and hybrid main-memory module, and propose a cross-layer cache design that (1) utilizes the information from the operating system to optimize the hit ratio of the DRAM cache inside the memory module, and (2) takes advantage of the bulk-size (or block-based) read/write feature of NVM to minimize the time overhead on the data movement between DRAM and NVM. At the same time, this cross-layer cache design is very lightweight and only introduces limited runtime management overheads. A series of experiments was conducted to evaluate the effectiveness of the proposed cross-layer cache design. The results show that the proposed design could improve access performance for up to 88%, compared to the investigated well-known page replacement algorithms.