Research of a Mixed-Signal Programmable SoC Based on FPAA

This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

Carrier generation and IF signal up-conversion using optical injection locking and stimulated Brillouin scattering

In this paper, the prototyping of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) has been presented. It summarily portrays the method implemented for configuration and reconfiguration of the proposed circuits by using Field Programmable Analog Array (FPAA). Their function was determined in the time domain at a constant 1 V supply voltages which is a sinewave input signal of 20 kHz frequency. The sampling frequency is fs = 4 MHz and the Oversampling ratio is OSR = 50 which yields a bandwidth of 40 kHz. Practical experimentation of the circuits was carried out using the AN221E04 FPAA device from Anadigm. Circuit realization of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) using FPAA are shown in figures. Also, sinusoidal input and output waveforms of implemented architectures are shown. A comparison of the proposed designed circuits with the various sigma-delta modulators published in the previous paper is also shown. The proposed sigma-delta modulators can be applied in the investigation and practical study of designing programmable analog devices and systems based on FPAA.

The noise simulation circuit of noncoherent spread-spectrum system intermediate frequency (IF) signal simulator is designed based on FPGA and DSP. This circuit generates white Gaussian noise (WGN), calculates coefficients of signal-to-noise ratio (SNR) refer to the specified SNR of each channel and according to these coefficients to generate spread-spectrum IF signal for transmitting to simulate the actual receive signal of responder beacon (RSP). It has been verified that the result of test meets the requests of system.

Phase-locked loops (PLL's) may be used to implement signal combiners which coherently sum multiple signals from an array of sensors. In each combiner channel, the sensor signal is simultaneously downconverted to an intermediate frequency (IF) signal and phase-locked to an appropriately generated reference signal by a "long-loop" PLL. This loop maintains a nominal 90° phase difference between the IF signal and the reference signal irrespective of phase of the channel input (sensor output) signal. The channel IF signals are summed to generate the combiner output signal. The reference signal may be a locally generated sine wave or a delayed version of the combiner output signal. Imperfect phase control and, thus, imperfect signal combining results when noise voltages are associated with the channel signals. In this paper, a lincarized model of a PLL coherent combiner is developed. This model applies when the desired channel signals are equal amplitude and angle modulated; the channel noise voltages are equal level, Gaussian distributed, and independent; and the combiner phase errors are appropriately small. This model is then used to derive equations for the variance of differential phase errors associated with combiner operation and to show the effect of these phase errors on the average power in the combiner output signal. Relevant experimental results from a four-channel combiner are compared with the performance predicted by the linear model.

We propose a photonic mixer with image rejection capability using a broadband optical source (BOS) and polarization processing. Intermediate frequency (IF) signals with image rejection are generated from the local oscillator-modulated and the time-delayed radio frequency (RF)-modulated BOS light. The RF operating frequency is flexibly tunable over a wide range by simply adjusting the time delay. In addition, the proposed system is free from dispersion-induced mixing power fading and bias drift problem. Experimental results exhibit an image rejection ratio of more than 44.6 dB for RF signals from 2 to 18 GHz, while the IF signal is fixed at 800 MHz. Image rejection mixing operation at different IF frequencies and signal power is also confirmed.

An image-rejected multi-band frequency down-conversion scheme is proposed and experimentally demonstrated based on photonic sampling. The multi-band radio-frequency (RF) signals to be processed are copied into two replicas in quadrature, which are then sampled by an ultra-short optical pulse train via a polarization-multiplexed modulator. After polarization demultiplexing and detection using a pair of low-speed photodetectors, the multi-band RF signals are simultaneously down-converted to the intermediate frequency (IF) band. The image components can be suppressed by quadrature coupling the two generated IF signals via an electrical 90° hybrid coupler (HC). In the experiment, multi-band RF signals in the frequency range of 6 GHz to 39 GHz are down-converted to the IF band below 4 GHz using a local oscillator (LO) signal at 8 GHz to generate the ultra-short optical pulse train. Image rejection is achieved in the digital domain using digital signal processing to compensate for the amplitude and phase mismatch between the two IF signals and to implement quadrature coupling. In addition, through using an electrical phase shifter, an electrical attenuator, and an electrical 90° HC to achieve quadrature coupling of the two IF signals, image-rejected multi-band frequency down-conversion is also verified in the analog domain.

We propose and experimentally demonstrate a photonic millimeter-wave frequency divider based on a super-harmonic injection-locked optoelectronic oscillator (OEO) and an optical frequency comb. The optical frequency comb generator is incorporated into an OEO loop to create broadband comb lines with low noise. By injecting a millimeter-wave with frequency around N times of the fundamental oscillating frequency f0 of the OEO, the injection signal can be down-converted to an intermediate frequency (IF) signal close to the oscillating frequency of the OEO. The free running OEO is synchronized with the IF signal via an injection locking mechanism. Consequently, it forms an injection-locked frequency divider as the frequency ratio between the injection signal and OEO's output signal is precisely equal to N. We carry out an experiment to divide the 45 GHz signal into 7.5 GHz and the experimental results agree well with the theoretical analysis. By changing the frequency of the injection signal, division ratio from 2 to 5 is also demonstrated on one setup. Due to the broadband spectra of the optical comb and low phase noise characteristics of the OEO, it is potential to realize very large division ratio and low phase noise for multiple input frequencies mf 0 .

Wideband photonic microwave channelization and image-reject down-conversion

A wireless transceiver typically uses a PLL at the transmitter to up-convert a baseband signal to an RF frequency and uses another PLL at the receiver to down-convert the RF signal back to the baseband. Depending on the quality of the PLL clock, which is often measured by its phase noise, the process of up-conversion and down-conversion produces unwanted signals which often interfere with signals in adjacent channels and deteriorate the SNR at the receiver. In this chapter, we first provide a brief background on the transmitter and receiver concepts, and then discuss the impact of PLL phase noise on transceiver performance. Basics of Wireless Transceivers Figure 8.1(a) shows the block diagram of a simplified wireless transmitter, in which a baseband signal is up-converted to an RF frequency in a two-step process: first to an intermediate frequency (IF), and then to an RF frequency, using a local oscillator (inside a PLL). The RF signal is then fed to a bandpass filter (BPF) followed by a power amplifier (PA) and the antenna. If the oscillator produces a pure single tone, the up-converted signal will simply contain the baseband signal translated (shifted) in frequency to f RF . If the baseband signal has a bandwidth of B, the RF signal will have a bandwidth of 2B, as shown in Figure 8.1(b). However, due to the phase noise of the oscillator, the up-converted signal will also contain frequency content outside the 2B bandwidth, which may contribute to noise in adjacent receiver channels. The BPF allows the signal and the noise content within the 2B bandwidth to pass but attenuates the phase noise and other noise content that lie outside the 2B bandwidth. The PA amplifies the power of the RF signal so as to extend its reach to the intended receivers. A simplified block diagram of a wireless receiver is shown in Figure 8.2(a). The received signal from the antenna is first filtered by an off-chip surface acoustic wave (SAW) filter, then passed to a low noise amplifier (LNA), and subsequently to a mixer that down-converts the RF signal either to an intermediate frequency (IF) or directly to DC for further filtering.

In this work, we propose an alternative for the circuital realization of analog fractional-order differentiators and integrators without using ladder networks. This alternative is obtained by a mathematical manipulation of a rational function in a similar way to the reported for the synthesis of the variable-state filters. The advantage of the proposed implementation is the requirement of only simple analog design blocks, such as integrators (of integer order), differential amplifiers and two-input adder amplifiers. Most important, contrarily to other reported solutions, the proposed realization can be fulfilled using commercially available resistors and capacitors, with a reduced number of calculations, and without negative impedance converters or inductors. In addition, the orders of the fractional derivative and integral can be modified just varying the gain of the differential amplifiers and adders. To validate the proposal of implementation, and as example of application, we present simulations (HSPICE, MATLAB) and experimental results of a first-order plus dead time plant controlled by fractional-order PI and PID controllers. The experimental results were obtained from a realization using field-programmable analog arrays. A comparison analysis highlights that the proposed alternative of implementation presents advantages regarding a Cauer-network-based realization in terms of number of active and passive elements, number of passive elements with non-commercial available values and design complexity.

This paper proposes three types of single stage low-power RF front-end, called double-balanced LMVs, by merging LNA, mixer, and voltage-controlled oscillator (VCO) exploiting a series <em>LC </em>(SLC) network. The low intermediate frequency (IF) or baseband signal can be directly sensed at the drain nodes of the VCO switching transistors by adding a simple resistor-capacitor (<em>RC</em>) low-pass filter (LPF). By adopting a double-balanced mixer topology, the strong leakage of the local oscillator (LO) at the IF output is effectively suppressed. Using a 65 nm CMOS technology, the proposed double-balanced LMVs (DB-LMVs) are designed. Oscillating at around 2.4 GHz ISM band, the phase noise of the proposed three DB-LMVs is −111 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain is larger than 36 dB and the double-side band (DSB) noise figure (NF) is less than 7.7 dB. The DB-LMVs consume only 0.2 mW <em>dc</em> power from 1-V supply voltage.

In the new 4K/8K satellite broadcasting, the maximum intermediate frequency (IF) is proposed to be changed from 2071 MHz to 3224 MHz. The coaxial cable has been widely used for IF signal transmission, but the attenuation is significant with a high signal loss when a high-frequency signal is transmitted. With the increasing number of 4K/8K channels and the development of broadcasting technology, the frequency used for the IF signal will keep increasing. Therefore, the coaxial cable may not meet the future ultra-high-definition satellite broadcasting requirements anymore. Compared to the all-electrical signal transmission, the Radio-over-Fiber (RoF) system can achieve signal transmission with lower loss and reduce noise sensitivity by transmitting the signal through an optical fiber. In this work, we propose a system that uses the RoF technology to reduce the signal loss during high-frequency transmission while adopting the Power-over-Fiber (PoF) technology to generate electric power for Low-Noise Block (LNB) and RoF unit on the antenna side. A method that combines the RoF technology and PoF technology into one Double-clad Fiber is also reported. With the comparison between the signal transmitted through an RoF system and that through a coaxial cable, it can be clearly shown that the advantage of the RoF technology in the signal loss performance. The experimental results of signal transfer demonstrate that by using the RoF technology, the average amplitude of the effective signal containing TV channels increases by 8.89 dB in the range of 2224-3224 MHz, while the average amplitude increases by 5.7 dB for the effective signal in the range of 1032-2071 MHz.

This paper reports on a Field Programmable Analog Array (FPAA) for high-frequency continuous-time analog filters. A rapid-prototyping hardware is presented, which implements a unique hexagonal topology of 55 tunable OTAs for reconfigurable instantiation of Gm-C filters in a 0.13 mum CMOS technology. It is the first analog array to achieve a bandwidth, which allows processing of intermediate frequencies used in communication systems. The maximum power dissipation is 70 mW at 1.2 V supply. The intuitive chip structure allows direct mapping of Gm-C filter schematics with up to 7 independent nodes, immediate download to the hardware, and evaluation of the working prototype.

Design of a low cost Schottky diode based single-balanced mixer (SBM) in full V-band with an ultra-wide intermediate frequency (IF) bandwidth is presented here. By loading multiple quarter-wavelength short-ended stubs at both radio frequency (RF) and local oscillator (LO) frequency on the multistage stepped impedance matching networks, a broadband grounding circuit is provided for IF signal and thus output power nulls are eliminated over an ultra-wide IF band. The hybrid network is constructed by a 3 dB branch coupler and a 90-degree delay line, which enables the required balanced outputs with equal amplitude and 180-degree phase difference. A prototype of the SBM is designed, fabricated and tested. Measured results demonstrate that, for RF and LO frequency over entire V-band, the mixer has a conversion loss from 6.8 to 11.4 dB with an ultra-wide IF range of 0.01–22 GHz.