Resource allocation and binding approach for low leakage power

The objective of this paper is to compare the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance .The MTCOS and SVL technique is used in 3T DRAM to compare the performance. Multi-threshold CMOS(MTCMOS) is a CMOS chip which has a Transistor with multiple threshold voltage and SVL is a technique which used to reduce leakage during both the active and stand-by mode. DRAM was first invented by Dr. Robert Dennard in the year 1966. It is used in many advanced processor for chip instruction and data memory. It majorly contributes in power dissipation in off-state leakage current. In personal computers it is used as the main memory, workstations etc. The basic advantage of using DRAM is its simplicity in its structure. Keyword- DRAM; FinFET; CMOS; Leakage power; Leakage current; Frequency; Access time; MTCMOS; SVL; USVL; LSVL

The intention of this paper is to reduce leakage power and leakage current of 1-bit Full Adder while maintaining the competitive performance with few transistors are used (transistors count 10). A new high performance 1-bit Full Adder based on new logic approach is presented in this paper. MTCMOS technique which decreases the process variation on 1-bit Full Adder, the key of MTCMOS technique is applied on 1-bit Full Adder is to reduce the operating power, leakage power and leakage current. We investigate the use Multi-threshold CMOS (MTCMOS) technology provides low leakage and high performance operation by utilizing high speed, low Vth transistors for logic cells and low leakage, high Vth of transistor and show that it is particularly effective in sub threshold circuits and can eliminate performance variations with Low power. A 20 ns access time and frequency 0.05 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out 1-bit Full Adder.

This paper presented a simulation result of current comparator with low power and low leakage current using Multi-Threshold CMOS technique (MTCMOS). In all integrated circuit power consumption plays a vital role which is enumerated as top challenges for semiconductor in international technology. In given paper designing a circuit of comparator with MTCMOS circuit and without MTCMOS circuit and then compared these circuits with different parameters by changing voltage, frequency and temperature. In these CMOS current comparator circuit different parameters calculated like delay, power dissipation, signal to noise ratio, leakage power and leakage current. The multi-threshold complementary metal oxide semiconductor technique is proposed to reduce the power consumption and leakage current. After propagating the circuit the leakage power is reduced 89% and leakage current 73% using MTCMOS technique. The new comparator has been in 180nm technology using cadence tool. The simulation and analytical result show that the proposed circuit is correct.

: The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

In modern ICs, sub-threshold voltage management plays a significant role due to its perspective on energy efficiency and speed performance. Level shifters (LSs) play a critical role in signal exchange among multiple voltage domains by ensuring signal integrity and the reliable operation of ICs. In this article, a Pass-Transistor-Enabled Split Input Voltage Level Shifter (PVLS) is designed for area, delay, and power-efficient applications with a wide voltage conversion range. The represented low-power LS structure is a general blend of both pull-up and pull-down networks that perform level-up or level-down shifts. The proposed PVLS is incorporated with the multi-threshold CMOS technique and a load-balancing driving split inverter to limit high static current, leakage power, and performance degradation. The schematic structure could be able to convert voltages from low to high as well as high to low. The architecture design has the lowest silicon area. The implementation of the proposed design was taken under 55 nm CMOS technology. The represented LS could be able to convert voltage ranges between 0.3 V and 1.3 V, which has a dynamic power of 2.00 nW. The overall propagation delay of the LS is 90 ps and an area of 7.66 µm2 for an input frequency of 1 MHz.

Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits

Analysis and Design of Subthreshold Leakage Power-aware Ripple Carry Adder at Circuit-level Using 90nm Technology

The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using deep submicron and nanometer technology, the peak power, peak power differential, average power and total energy are equally critical design constraints. In this work, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power while maintaining performance by use of dynamic frequency clocking and multiple supply voltages. The algorithms use integer linear programming based models. The dynamic frequency clocking methodology is more useful for data intensive signal processing applications. The effectiveness of our scheduling technique is measured by estimating the peak power consumption, the average power consumption and the power delay product of the datapath circuit. Furthermore, the proposed scheduling scheme is compared with combined multiple supply voltages and multicycling scheme. Experimental results show that combined multiple supply voltages (3.3V,2.4V) and dynamic frequency clocking scheme achieves significant reductions in peak power (72% on the average), average power (71% on the average) and power delay product (54% on the average).

Experimental Investigation of Waste Vegetable Oil – Diesel Fuel Blends Effects on Performance of Compression Ignition Engine

In CMOS technology, performance degradation of power is one of the foremost questions at daily vitality. In this circuit, power dissipation is increasing exponentially constantly with technology scaling down. The analog to digital converters (ADCs) are the vital branch of signal processing and communication system. In digital region power consumption and low voltage develop into wide component is difficult for conniving high speed devices and converters. In this paper we have presented a complete investigation of 3 bits flash ADC circuit by using low leakage stacked power gating technique and diode based stacked power gating technique. These techniques are reduces the leakage current and average power in standby mode effectively. In this circuit, with the stacked power gating technique, leakage current and average power is reduced is by up to 77% and 99% respectively. Diode based stacked power gating technique can be identified as the most effective technique. With this technique, leakage current is 1.241 nA at 0.7 V and average power is 3.49 nW at 0.7 V. To evaluate of power gating techniques, the simulation has been performed using cadence virtuoso tool at assorted power supply by 45nm technology.

Multi-threshold CMOS (MTCMOS) is the most widely used circuit technique for suppressing subthreshold leakage currents in idle circuits. When a conventional MTCMOS circuit transitions from SLEEP mode to ACTIVE mode, voltages of power and ground distribution networks are disturbed. Mode transition noise phenomenon in MTCMOS circuits is examined in this chapter. An MTCMOS circuit technique with three operating modes (tri-mode) is described for noise suppression during activation events. A threshold voltage tuning methodology is presented to further alleviate the mode transition noise with smaller sleep transistors in MTCMOS circuits. Alternative applications of tri-mode MTCMOS for data preservation and leakage power reduction in idle memory elements are also discussed.

Quantum mechanical principles that govern the basic laws of physics increasingly limit CMOS operation with transistor scaling. Traditional logic based CMOS circuits cannot achieve ultra-low power levels due to heat dissipated for a single bit loss of information as represented by the Landauer barrier. Reversible logic is a promising computing paradigm towards realization of ultra-low power computing circuits. Reducing average and peak power consumption is an effective strategy for mitigation of side-channel attacks, such as Differential Power Analysis. We present designs of Forward Body Biased Adiabatic Logic for reduction of average, peak, and differential power. HSPICE simulations with predictive 22nm technology are used to analyze performance metrics and exhaustive simulation results are presented for various reversible CMOS designs. Average power is improved upon by up to 91%, the peak power by up to 96%, and the differential power is improved by up to a factor of 128.57.

Recent trends in CMOS technology and scaling of devices clearly indicate that leakage power in digital circuits would be crucial and largely depend on the sub-threshold currents. Minimizing leakage, by power gating logic circuits using sleep transistors gives considerable power savings. However, this technique cannot be used in sequential circuits and memory cells, as it would result in loss of stored data. In this paper, we propose a novel circuit by applying a self-bias transistor (SBT) to minimize sub-threshold leakage currents in static and dynamic circuits. This circuit with SBTs, acts as a smart switch by virtually power gating either pull-up or pull-down logic, and causes a considerable reduction in leakage currents in both active and standby modes. A benchmark is simulated with 0.18 /spl mu/m CMOS technology in the Cadence Spectre circuit simulator. Results show significant reduction in leakage power, of up to 50% on average, for all possible states simulated in static and dynamic circuits by applying this proposed self-bias transistor.

The subthreshold and gate oxide leakage power characteristics of domino logic circuits are evaluated in this paper. The preferred input vectors and node voltage states are identified to minimize the total leakage power consumption in the sleep mode. New low leakage design guidelines based on the results are presented. Previous studies indicate that a discharged dynamic node voltage state with high inputs is preferable to reduce the subthreshold leakage power consumption in an idle dual threshold voltage domino gate. However, the gate oxide leakage is ignored in the previous studies. The significantly increased gate dielectric tunneling current, as described in this paper, shifts the leakage power characteristics of dynamic circuits in the sub-65nm CMOS technologies. Contrary to the previously published techniques in older technologies, a charged dynamic node voltage state with low inputs is preferred for reducing the total leakage power consumption in the wide fan-in dual threshold voltage domino gates. Similarly, a charged dynamic node voltage state with low inputs is preferred for lowering the leakage power consumption in all types of low threshold voltage domino gates in a 45nm CMOS technology

An adder is one of the main components in many digital devices, DSP processors, etc. Leakage power reduction and area have become important factors in designing recent VLSI circuits. As the technology is constantly scaling down, threshold voltage of transistors is also reduced, thereby making the static power dissipation high. In this paper a low power 10T full adder is designed in 45 nm complementary pass transistor technology. Power dissipation and delay are compared with the conventional 28 transistor full adder, proposed 10 transistor full adder, Multi Threshold CMOS (MTCMOS) based 28 transistor full adder and proposed Multi Threshold based 10 transistor full adder. Compared to the conventional 28 transistor full adder, the proposed design shows power dissipation is reduced by 99.528% and Power Delay Product (PDP) by 99.913%. The proposed circuit reduces the area used by 64% accompanied with high speed of operation.