Restrained Latency Universal Modulator Outlay Adaptive CORDIC Algorithm for Digital Communication

This paper presents the fast and area efficient CORDIC (Coordinate Rotation DIgital Computer)algorithm for sine and cosine wave generation. The concepts of pipelining and multiplexer based CORDIC algorithm is used todecrease the critical path delay and reducing the area respectively. A six stage CORDIC is implemented by two schemes followed by four methods, unrolled CORDIC and multiplexer based CORDIC with and without pipelining. The pipelining is included in four stages(excluding first and last stage). An 8-bit CORDIC algorithm for generating sine wave and cosine wave is designed, implementedand compared by all four methods on Xilinx Spartan3E (XC3S250E).

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

In response to the limitations of insufficient reconfigurability and excessive hardware resource overhead associated with traditional FFT circuits in multi-standard signal processing scenarios, this paper proposes a reconfigurable mixedradix FFT circuit design grounded in the CORDIC (Coordinate Rotation Digital Computer) algorithm. This design employs a hybrid basis $(2 / 3 / 4 / 5)$ decomposition structure, enabling the reconfigurable computation of FFTs with varying point counts through the dynamic configuration of computational units. An enhanced CORDIC algorithm is implemented in the rotation factor generation module, where an optimized set of rotation angles is utilized. This method effectively reduces hardware resource consumption and latency while ensuring computational accuracy. Simulation and experimental results conducted on an FPGA platform demonstrate that the design achieves a computational signal-to-noise ratio (SNR) of at least 60 dB, thereby meeting the precision requirements of most communication systems. When compared to similar FFT circuits, this design significantly decreases hardware resource utilization while maintaining comparable computational speed, resulting in an approximate power savings of $\mathbf{4 4\%}$. Keywords-Mixed-Radix FFT CORDIC Reconfigurable

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.

The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.

There exist a number of algorithms to map the phase to amplitude in direct digital synthesis (DDS). For DDS with more than 14 output bits, the Coordinate Rotation Digital Computer (CORDIC) algorithm is well known for its high precision. Also, it is effective in solutions where there is the need of in-phase and quadrature components simultaneously because the algorithm calculates both. In this paper, a Taylor expansion based method was proposed to calculate both in-phase and quadrature at the same time. Numerical simulations for different data format, e.g., double and finite bits, were carried out in Matlab and Quartus, which were followed by the hardware implementation in Field Programmable Gate Array. The results demonstrated that the proposed method possessed higher precision and exhausted less logic elements than the CORDIC algorithm.

The improved coordinate rotation digital computer (CORDIC) algorithm gives high precision and resolution phase rotation, but it has some shortages such as high iterations and big system delay. This paper puts forward unidirectional rotating CORDIC algorithm to solve these problems. First, using under-damping theory, a part of unidirectional phase rotations is carried out. Then, the threshold value of angle is determined based on phase rotation estimation method. Finally, rotation phase estimation completes the rest angle iterations. Furthermore, the paper simulates and implements the numerical control oscillator by Quartus II software and Modelsim software. According to the experimental results, the algorithm reduces iterations and judgment of sign bit, so that it decreases system delay and resource utilization and improves the throughput. We always analyze the error brought by this algorithm. It turned out that the algorithm has a good application prospect in global navigation satellite system and channelized receiver.

This paper presents the implementation of KA algorithm and Coordinate Rotation Digital Computer (CORDIC) structures for adaptive digital signal processing. Adaptive FIR filter is used in RADAR to detect weak RADAR signal. Implementation of FIR Adaptive filter requires more hardware and power consumption. Several optimization techniques are proposed to reduce hardware, power consumption and increase the speed. The optimization algorithm used in FIR Adaptive filter are Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm CORDIC algorithm are widely used in RADAR application due to it's simple architecture and processor independent nature. CORDIC structures are implemented using shifter and adder. Compared to MAC unit CORDIC structures have less chip area and high speed. Further the speed and chip area of CORDIC structure is improved by combining CORDIC with KA architecture. The larger computation is splitted into smaller computation unit using KA algorithm and the computation operation is performed without multiplier using CORDIC structures, hence overall speed and chip area are improved.

Objective: The objective of this work is to efficiently implement a Co-ordinate Rotation Digital Computer (CORDIC) based fast algorithm for power of two length DCT. Methods: The proposed algorithm has some advantages such as regular Cooley-Tukey FFT like data flow, post scaling factor and arithmetic-sequence rotation angles. Using CORDIC algorithm, different types of DCT like four point, eight point and inverse eight point are derived. Usage of trigonometric formula reduces the number of CORDIC. By reusing uniform processing Element cells, architecture for 8-point CORDIC DCT is developed. This is an efficient method for overcoming the problem of lack of synchronization among various rotation angles. Findings: When compared with other known architectures, the proposed 8-point DCT architecture is more efficient in terms of power and area. Power analysis and area estimation are performed for the designed architectures and then further power reduction is carried out using clock gating technique. A power reduction of 4.29% is achieved. The area is also reduced by 0.29%. Conclusion: An efficient VLSI implementation for 8-point DCT by reusing the uniform processing element cells with low hardware complexity is developed.

The Coordinate Rotational Digital Computer (CORDIC) algorithm allows computation of trigonometric, hyperbolic, natural log and square root functions. This iterative algorithm uses only shift and add operations to converge. Multiple fixed radix variants of the algorithm have been implemented on hardware. These have demonstrated faster convergence at the expense of reduced accuracy. High radix adaptive variants of CORDIC also exist in literature. These allow for faster convergence at the expense of hardware multipliers in the datapath without compromising on the accuracy of the results. This paper proposes a 12 stage deep pipeline architecture to implement a high radix adaptive CORDIC algorithm. It employs floating point multipliers in place of the conventional shift and add architecture of fixed radix CORDIC. This design has been synthesised on a FPGA board to act as a coprocessor. The paper also studies the power, latency and accuracy of this implementation.

The hardware implementation of a magnitude estimation algorithm for a hearing aid is presented in this paper. Digital signal processing (DSP) is used in almost all the modern digital hearing aids available today. The processing of the sound signals is carried out in the frequency domain. Fast Fourier transform (FFT) converts the time domain signal to frequency domain and gives a complex number output representing each frequency component in the audible frequency spectrum. The magnitude estimation block estimates the magnitude of these complex numbers. This estimated magnitude is used as an input to apply various DSP algorithms for sound processing in the hearing aid. In this paper the Alpha max-Beta min and the coordinate rotation digital computer (CORDIC) algorithms for magnitude estimation of a complex number are compared from the hardware implementation point of view. The emphasis of this paper is the hardware implementation of the CORDIC algorithm in application specific integrated circuit (ASIC) design flow and its performance analysis. The CORDIC algorithm is implemented because of its accuracy and implementation simplicity. The paper also presents the simulation and synthesis results obtained for hardware implementation of four iterations of the CORDIC algorithm for magnitude estimation.

Wireless mobile receivers and hand-held terminals have experienced tremendous growth. Especially, DAMPS (Digital American Mobile Phone System) has a tremendous market share in the cellular phone community. Mobile receiver designers feel the need to keep the cost of design low while maintaining a high performance, and to have a digital sub-system which uses DSP algorithms to provide immunity to multipath fading problem. A novel approach for VLSI realization of a reduced complexity of CORDIC (coordinate rotation digital computer) algorithm for DAMPS or a digital IF-sampled receiver is presented. It is intended to be suitable for the inexpensive realization of a demodulator, which is part of the D-AMPS modem within a VLSI chip. The reduced complexity CORDIC algorithm offers several advantages. First, it only uses one barrel shifter compared to the method of Chen, McDanell, Boytim and Pogue (see Proceedings IEEE Globecom, Singapore, 1995) with two barrel shifters. Also, the barrel shifter only needs to provide even shifts in the algorithm. Second, with a small input data, it can avoid the numerical problem. The scaling factors can be computed at the end of the CORDIC iterations instead of at every iteration. Overall, the algorithm is computationally efficient and conceptually simple with half complexity of previous schemes.

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms, square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation.

The COordinate Rotation DIgital Computer (CORDIC) algorithm is a famous technique for realizing complex arithmetic functions using simple shift-add operations. This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for high performance hyperbolic computations. We target algorithm level improvements to achieve low area and power-delay product on FPGA. Instead of complex search algorithms, we use the most significant one bit detection technique for micro-rotation sequence identification, which helps in significantly reducing the number of pipelining stages. The proposed technique uses mathematical identities to extend the range of convergence. The eight-staged pipelined architecture implementation requires a ROM in the preprocessing unit for storing the initial coordinate values, while the ROM for storing the elementary angles is eliminated. The FPGA implementation of the proposed processor requires 46.35% less gates and has 31.81% less delay when compared with Xilinx Core IP-CORDIC v3.0. Moreover, on an average it consumes 75.96% less power when compared with Xilinx CORDIC v3.0. Hence, the proposed technique provides an area–power-delay efficient VLSI implementation for calculating hyperbolic functions and exponents. The detailed algorithm design, along with FPGA implementation and area and time complexities, is presented in this paper.