Reversible Logic based Cryptography Design Algorithm using Random Keys

The Reversible logic gates implement the functions which are having one to one mapping between the input and output. Unlike irreversible logic circuits the information cannot be lost as the input vector can be recovered from the corresponding output vector. The dissipation of heat is also less in reversible logic gates. Therefore the reversible logic gates have immense number of applications in Low power CMOS design, quantum computing, Nano technology and digital signal processing. This paper proposes a novel 4×4 bit reversible fault tolerant MAC unit. The MAC unit Composed of a multiplier, adder and an accumulation unit. The Ripple Carry Adder and multiplier used in the proposed work were designed using parity preserving gates. The basic building blocks for adder and multiplier used were IG gate, Fredkin gate which are parity preserving gates. Therefore the proposed MAC unit has characteristic attribute of detecting any errors in output side. The synthesis and simulation was done by using Xilinx software and Model Sim Simulator.

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

Digital Signal Processing (DSP) applications in Bioinformatics have received great attention in recent years, where new effective methods for genomic sequence analysis, such as the detection of coding regions, have been developed. The use of DSP principles to analyze genomic sequences requires defining an adequate representation of the nucleotide bases by numerical values, converting the nucleotide sequences into time series. Once this has been done, all the mathematical tools usually employed in DSP are used in solving tasks such as identification of protein coding DNA regions, identification of reading frames, and others. In this article we present an overview of the most relevant applications of DSP algorithms in the analysis of genomic sequences, showing the main results obtained by using these techniques, analyzing their relative advantages and drawbacks, and providing relevant examples. We finally analyze some perspectives of DSP in Bioinformatics, considering recent research results on algebraic structures of the genetic code, which suggest other new DSP applications in this field, as well as the new field of Genomic Signal Processing.

Finite Impulse Response (FIR) Filter occupied a significant position in most of Digital Signal Processing (DSP) Applications. The behaviour of FIR filters can be realized in software for DSP applications and executed on Digital Signal Processor architectures. These kinds of digital filters consider digital components, digital input and perform mathematical computations to produce digital output. In modern DSP applications demanding area efficient architecture for DSP algorithms while optimizing throughput. This can be achieved by design of hardware architectures for DSP algorithms and apply design optimization techniques to accelerate the throughput and minimize area. This article attempts to develop hardware architectures for FIR Filter and apply the design optimization techniques present in literature. In this article, High Level Synthesis concepts were adapted to develop hardware architecture for FIR filter and optimization techniques have been applied to optimize design attributes like area, throughput and power. Finally, design attributes are summarized after applying optimization techniques and published significant architectural attributes suitable for real life DSP applications.

Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. As our day to day life is demanding more and more portable electronic devices, challenging focus on technology is demanding great system performance without any compromise in power consumption. It is obvious to find tradeoff between processing power and heat generation. As decreased processing speed leads to reduced power consumption but obviously compromise in performance is not acceptable for sophisticated applications. Thus power consumption is a prime target now days. Needless to say, researchers will now look at reversible logic in this vein. Primitive component of reversible logic synthesis are reversible logic gates. Thus it is very important for a new researcher to look into extensive literature survey of reversible logic gates. Many papers have been reported with review of reversible logic gates. This paper aims on updates in reversible logic gates which are stepping stones in design and synthesis of any complex reversible logic based synthesis.

Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. As our day to day life is demanding more and more portable electronic devices, challenging focus on technology is demanding great system performance without any compromise in power consumption. It is obvious to find tradeoff between processing power and heat generation. As decreased processing speed leads to reduced power consumption but obviously compromise in performance is not acceptable for sophisticated applications. Thus power consumption is a prime target now days. Needless to say, researchers will now look at reversible logic in this vein. Primitive component of reversible logic synthesis are reversible logic gates .Thus it is very important for a new researcher to look into extensive literature survey of reversible logic gates. Many papers have been reported with review of reversible logic gates. This paper aims on updates in reversible logic gates and propose a novel reversible DS gate which will be stepping stone in design and synthesis of any complex reversible logic based synthesis.

The rapid increase in digital signal processing (DSP) applications has generated a strong demand for electrical engineers with DSP backgrounds; however, the gap between industry needs and university curricula still exists. To answer this challenge, a sequence of innovative DSP courses that emphasize hands-on experiments and practical applications were developed for continuing education in electrical and computer engineering. These courses are taught in the evening for night-school students having at least three years of work experience. These courses enable students to experiment with sophisticated DSP applications to augment the theoretical, conceptual, and analytical materials provided in traditional DSP courses. The inclusion of both software and hardware developments allows students to undertake a wide range of DSP projects for real-world applications. Assessment data concludes that the digital signal processor fundamentals course can increase learning interest and overcome the prerequisite problem of DSP laboratory experiments. This paper also briefly introduces representative examples of some challenging DSP applications.

Signal processing has always been a critical aspect of interferometric spectroscopy. The main value of Fourier Transform Spectroscopy (FTS) is to provide the maximum information per unit time. This means that careful signal processing is required to maximize the signal to noise ratio of the result. Digital signal processing (DSP) is not new in FTS. DSP for apodization, Fourier transform, phase correction, and some digital filtering have been used for many years. The first difficulty encountered in using DSP is the required transformation of the continuous time signal to a sequence of finite precision numbers, that is a discrete time, discrete magnitude representation of the continuous signal. Today, sampling and digitization with conventional techniques are reasonably straightforward, with digitization noise of the order of 2−16. Advances in several aspects of FTS technology, including step scanning, have created the need to lower the digitization noise. The processing of signals from multiple modulation FTS experiments, specially step-scan signals, has presented serious limitations until recently, due primarily to the performance restrictions of the available hardware, and the fundamental limitations of the analog systems used. The application of DSP techniques to reduce the sampling and digitization errors are reviewed, and practical solutions that can provide digitization noise lower than 2−24 with low cost systems are described. Some of the causes and effects of sampling error are reviewed, to clarify common misunderstandings. DSP applications in the detection of multiple modulation step-scan experiments and photoacoustic spectroscopy are described in detail. These applications allow the measurement of the signal during the entire step time, eliminate interference of secondary effects of phase modulation, and integrate the entire experiment in the data system, eliminating all the analog adjustments (knobs) needed when lock-in amplifiers are used.

The aim of this contribution is first to show how the Szego theory of orthogonal polynomials on the unit circle is intimately related to the celebrated Levinson algorithm, which is commonly used in digital signal processing (DSP) applications to solve various least-squares problems. A computationally more efficient substitute for the Levinson algorithm, termed the split Levinson algorithm, has recently been proposed in the DSP literature. In the case of real data, this new algorithm can be interpreted naturally in the framework of a well-defined one-to-one correspondence between the families of real Szego polynomials and the families of polynomials orthogonal on the interval [-1, 1] with respect to a symmetric measure. More generally, the philosophy underlying the split Levinson algorithm opens the door to an interesting “tridiagonal approach” to the theory of complex Szego polynomials, nonnegative definite Hermitian Toeplitz matrices, and related algebraic and function theoretic questions. Some of the main topics of this new mathematical framework are briefly reviewed and are shown on specific examples to be of particular interest in DSP applications.

This work presents an analysis of power efficiency in microprocessor architectures targeting wide-range digital signal processing (DSP) applications. We defined a circuit level power estimation technique based on the integration of traditional analytical power models so as to account for both block-internal and interconnects-dependent dissipation and we extended it to provide applicability to specific DSP-related structures. We applied the modeling approach to several architecture schemes and demonstrated that a relatively novel solution, namely the transfer triggered architecture, can be the most power-efficient scheme in DSP applications.

Heat is an important issue in VLSI circuits. But the reversible logic gives zero amount of heat dissipation. So, its an important role in nanotechnology, less energy complementary metal oxide semiconductor [CMOS] designs etc. It has been realized that quantum computing is one of the latest technologies using reversible logic gates. It is contemplating that accumulation extension of transistor density, energy desolation will command their limits in ordinary technologies. In ordinary area or range during the logic influence bits of orientation is erased resulting gratification of power in powerful amount. In the terms of reversible logic results are not lost.[1] This minimize the delays but at the amount of little hardware. So we can use reversible logic technology for decreasing the energy dispersion, heatwave dissipation, increasing rapidness etc. So it is used to maximize the speed and reducing energy consumption. In this, we can describe following reversible logic gates like fredkin, peres, Feynmen and toffoli gate etc.

Reversible or information-lossless circuits have applications in digital signal processing, communication, computer graphics and cryptography. Reversibility plays an important role when energy efficient computations are considered. Reversible logic is used to reduce the power dissipation that occurs in classical circuits by preventing the loss of information. This paper proposes a reversible design of a 16 bit ALU. This ALU consists of eight operations, three arithmetic and five logical operations. The arithmetic operations include addition, subtraction, multiplication and the logical operations include NAND, AND, OR, NOT and XOR. All the modules are being designed using the basic reversible gates. The power and delay analysis of the various sub modules is performed and a comparison with the traditional circuits is also carried out.

An efficient and energy-aware design of a novel nano-scale reversible adder using a quantum-based platform

The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

Wireless sensor network (WSN) applications have been studied extensively in recent years. Such applications involve resource-limited embedded sensor nodes that have small size and low power requirements. Based on the need for extended network lifetimes in WSNs in terms of energy use, the energy efficiency of computation and communication operations in the sensor nodes becomes critical. Digital Signal Processing (DSP) applications typically require intensive data processing operations and as a result are difficult to implement directly in resource-limited WSNs. In this article, we present a novel design methodology for modeling and implementing computationally intensive DSP applications applied to wireless sensor networks. This methodology explores efficient modeling techniques for DSP applications, including data sensing and processing; derives formulations of Energy-Driven Partitioning (EDP) for distributing such applications across wireless sensor networks; and develops efficient heuristic algorithms for finding partitioning results that maximize the network lifetime. To address such an energy-driven partitioning problem, this article provides a new way of aggregating data and reducing communication traffic among nodes based on application analysis. By considering low data token delivery points and the distribution of computation in the application, our approach finds energy-efficient trade-offs between data communication and computation.