Revisiting the doping requirement for low power junctionless MOSFETs

In this work, through calibrated simulations, comparative analysis of n-type Negative Capacitance (NC) Junctionless (JL) and Inversion Mode (IM) transistor is performed for Low Power (LP) applications. Through systematic metholdology and physical insights, it is highlighted that NC JL device exhbits negative internal gate voltage (V int ) at zero applied external gate bias (V gs ), which is benefical to achieve significantly lower value of off-current (I off ) than NC IM device for LP applications. It is demonstrated that negative V int in NC JL device can further be utilized to lower the gate workfunction to mid-gap level while achieving the and I on ~ 1.3 mA/μm at lower I off ~ 10 pA/μm. The work showcases the opportunites to achieve the International Roadmap for Devices and Systems (IRDS) traget at gate length (L g ) of 20 nm and drain bias (V ds ) of 0.1 V for designing LP systems and circuits using NC JL transistor.

Drain breakdown voltage: A comparison between junctionless and inversion mode p-channel MOSFETs

This brief investigates short-channel effects (SCEs) in junctionless (JL) double-gate (DG) MOSFETs analytically by solving the 2-D potential in subthreshold. Ids-Vg curves and Vt rolloff generated from the model are validated by 2-D numerical simulations (Technology Computer Aided Design). It is shown that the SCE of JL MOSFETs is inherently worse than that of undoped DG MOSFETs. The SCE worsens with increasing doping concentration in the channel.

Impact ionization induced dynamic floating body effect in junctionless transistors

The temperature effects of both gate-all-around polycrystalline silicon nanowire (GAA poly-Si NW) junctionless (JL) and inversion mode (IM) transistor devices at various temperatures (77–410 K) were investigated. The electrical characteristics of these devices, such as subthreshold swing (SS), threshold voltage (Vth), and drain-induced barrier lowering (DIBL), were also characterized and compared in this study. Moreover, JL devices with different doping concentrations at various temperatures were also discussed. Both Vth and Ion showed significant doping concentration dependences for JL devices with doping concentrations of 1 × 1019 and 5 × 1019 cm−3. However, the electrical characteristics of JL devices showed less thermal sensitivity when the doping concentration reached 1020 cm−3.

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wider bandgap p-type In0.52Al0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a JL MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm2/V·s at Nd = 1×1019 cm-3, while in In0.53Ga0.47As the bulk mobility is ~4,000 cm2/V·s at a similar Nd level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n- In0.53Ga0.47As (Nd = 2×1018 cm-3) on a 500-nm-thick p-In0.52Al0.48As (Na = 8×1015 cm-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In0.53Ga0.47As layer was thinned using a 10% H2O2/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH4)2S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al2O3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H2+90%N2) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2]. Well behaved Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel device are shown in Fig. 2. A threshold voltage (VT) of -0.55 V was extracted using the second-derivative method. Scaling the In0.53Ga0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In0.53Ga0.47As channel device and 190 mV/dec - on the 24-nm-thick In0.53Ga0.47As channel one, but the highest ION/IOFF value (1.5×105) was obtained on the 20-nm-thick In0.53Ga0.47As channel device and 2.0×104 - on the 24-nm-thick In0.53Ga0.47As channel one. The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap. Moreover, the conductance analysis yielded low Dit values ranging from 1.5×1012 to 3.5×1012 cm-2×eV-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In0.53Ga0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm2 at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the ION by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of Dit and negative charge in the gate dielectric. The conductance analysis yielded reduction of Dit at midgap down to 1.0×1012 cm-2×eV-1. [1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010). [2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008). Figure 1

In this paper, we report on the anomalous behavior of threshold voltage ( ${V} _{\sf th})$ with temperature in junctionless (JL) transistors. It is shown that both positive and negative values of temperature coefficient of threshold voltage ( dV $_{\sf th}$ / dT ) in nMOS Si and Ge JL devices can occur at higher drain biases. At lower temperatures, ${V} _{\sf th}$ reduces with a decrease in temperature due to the dominance of bipolar effects over thermal generation of carriers, whereas at higher temperatures, thermal generation results in essentially unipolar characteristics, and ${V} _{\sf th}$ reduces with increase in temperature. It is also shown that zero temperature coefficient condition shall be nonexistent under dominant bipolar conduction over unipolar operation. Results show new viewpoints to understand the two contrasting physical mechanisms leading to positive and negative dV $_{\sf th}$ / dT values in JL devices.

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

In this work, the impact of gate material work function on the sensitivity of dual-material, double-gate, junctionless MOSFET ( $$DMDG-JL-MOSFET$$ )-based biosensor has been studied. To enhance the sensitivity of the biosensor, optimization of gate work functions has been done through Sentaurus TCAD simulator. With the immobilization of biomolecules in the cavity at different value of work function of gate metal 1 (M1) and gate metal 2 (M2), i.e., WF1 and WF2, enhancement in sensing metrics (change in threshold voltage $$S_{V{\rm th}}$$ and $$I_{ON}$$ / $$I_{OFF}$$ ratio) is observed. The enhancement in sensitivity is profound in source-side gate (M1) work function (WF1) optimization as compared to drain-side gate (M2) work function (WF2) optimization. Sensitivity of 90 mV is observed in source-side gate work function optimization which is $$\sim$$ 89% more than the sensitivity of 23 mV which is achieved in drain-side gate work function optimization for a fixed concentration and dielectric constant of biomolecules. It has also been noted that the proposed structure exhibits $$\sim 90\%$$ higher sensitivity than the single-material, dual-gate, junctionless MOSFET ( $$SMDG-JL-MOSFET$$ ) biosensor. Results showcase that the optimization of gate metal work functions enhances the sensitivity of the biosensor.

In this paper, a new junctionless optical controlled field effect transistor (JL-OCFET) is proposed to improve the device performance as well as achieving low power consumption. An overall optical and electrical performances comparison of the proposed junctionless design and the conventional inversion mode structure (IM-OCFET) has been developed numerically, to assess the optical modulation behavior of the OCFET for low power optical interconnections applications. It is found that, the proposed design demonstrates excellent capability in decreasing the phototransistor power consumption for inter-chip optical communication application. Moreover, the proposed device offers superior sensitivity and I ON /I OFF ratio, in addition to lower signal to noise ratio as compared to the conventional IM-OCFET structure. The obtained results indicate the crucial role of the junctionless (JL) design in enhancing the phototransistor performance and reducing the total power dissipation. Such a very sensitive OCFET can be very promising in the future low power optical receiver less compatible to CMOS modern technology for high-quality inter-chips data communication applications.

The Double gate (DG) silicon on insulator (SOI) metal oxide field effect transistor (MOSFET) is the leading contender for sub 100nm devices. This paper presents a systematic study of effect of work function of metal gates on symmetric double-gate (DG) MOSFET. Two-dimensional simulation tools are used to investigate the effect of work function of gates on Double gate MOSFET. From simulation we observed that by changing the work function of the metal gates of Double gate MOSFET we can change the threshold voltage. Hence by using this technique we can set the appropriate threshold voltage of DG MOSFET at same voltage and we can decrease the leakage current and short channel effects.

Energy band tails and photoconductivity

The characteristics of junctionless(JL) SON(Silicon on Nothing) FinFET, JL Bulk FinFET and SOI(Silicon on Insulator) JNT(Junctionless nanowire transistor) transistors were compared. A Silicon on nothing transistor have substrate with air filled dielectric. JL SON FinFET have better on/off current ratio and short channel effect (SCE) by reducing channel thickness due to substrate channel junction. The subthreshold slope is 63.2m V/dec and DIBL 82.68mV. the on/off current ratio is approximately 105 at channel thickness of 10nm. The variation in threshold voltage as Nsub varies from 1017 to 1018 cm−3 is about 33%. JL SON FinFET gives better on/off current ratio with the variation of work function.

A diode has been realised using a silicon junctionless (JL) transistor. The device contains neither PN junction nor Schottky junction. The device is measured at different temperatures. The characteristics of the JL diode are essentially identical to those of a regular PN junction diode. The JL diode has an on/off current ratio of 108, an ideality factor of 1.09, and a reverse leakage current of 1 × 10−14 A at room temperature. The mechanism of the leakage current is discussed using the activation energy (EA). The turn-on voltage of the device can be tuned by JL transistor threshold voltage.

In this paper, we report the logic performance of CMOS circuits implemented with n- and p-channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made between such circuits and those implemented with n- and p-channel conventional inversion-mode (IM) FinFETs. The logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators. Frequency of oscillation of a three-stage ring oscillator (RO) is also obtained for such nodes. In spite of reduced ON-state current arising out of the higher channel doping and, hence, reduced carrier mobility in the JL devices, somewhat improved performance of the JL CMOS circuits over their IM counterparts are observed. For example, improvement of ~28% and ~10% in the rise time and fall time, respectively, for the inverter and ~12% in the frequency of oscillation of RO are observed for 10-nm technology node. Our investigations reveal reduced gate capacitance of the JL devices that in turn result in such improved performance of the JL CMOS circuits. Reduced gate capacitance also results in reduced dynamic power dissipation of JL CMOS circuits.