Revisiting the linear programming framework for leakage power vs. performance optimization

If current technology scaling trends hold, leakage power dissipation soon becomes the dominant source of power consumption. Caches, due to the fact that they account for the largest fraction of on-chip transistors in most modern processors, are a primary candidate for attacking the leakage problem. While there has been a flurry of research in this area over the last several years, a major question remains unanswered. What is the total potential of existing architectural and circuit techniques to address this important design concern? In this paper, we explore the limits in which existing circuit and architecture technologies may address this growing problem. We find that by using perfect knowledge of the address trace to carefully apply sleep and drowsy modes, the total leakage power from the instruction cache may be reduced to mere 3.6% of the unoptimized case, and the total from the data cache reduced to only 0.9%. We also present a complete parameterized model to determine the optimal leakage savings while the implementation technology changes over time. We further suggest how such limits might be approached using a form of prefetching for low power.

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

For low-power designs utilizing multiple threshold voltage (VT) levels such as using a mixture of regular, low, and super-low VT standard cells, a small perturbation on each VT level leads to a significant fluctuation of the leakage power consumption. In this context, this work addresses the problem of finding the value of each VT level on the target design with the objective of minimizing the total leakage power consumption of the design. Precisely, for a timing closed design, typically at the post-route stage, whose leakage power has already been optimized for a representative (i.e., nominal) value of each VT level, we explore the range of VT level values and fine-tune the VT values, so that the resulting leakage power of the design should be further minimized while not violating the timing constraints. To this end, we propose a near-optimal approximation technique based on a piecewise-linear programming formulation for the VT reassignment, incorporating the practical issue of circuit delay and leakage power recalculation incurred by VT tuning into linear programming constraints and objective. In the meantime, through experiments with benchmark circuits, it is shown that our VT tuning technique is five orders of magnitude faster than the conventional VT tuning while further reducing the leakage power by 5.41% under the circuit timing constraints.

The proliferation of high performance processors has been enabled by shrinking feature sizes in CMOS technology. This reduction in feature sizes enables designers to scale down the supply and threshold voltages accordingly. Although reduced threshold voltage improves the speed of the devices, it also leads to increased static power dissipation. In this paper, the static leakage power characteristics of CMOS multiplier circuits are analyzed as they are the most expensive and slow units in the datapath of a microprocessor. Each of the multipliers (carry-save, bit-array, and Wallace) is implemented at two different technology sizes (65 nm and 45 nm) realized using three different full adders (10 Transistor (10 T) adder, Static energy recovery full adder and Mirror adders). Among the three multipliers, the carry-save multiplier consumed maximum leakage current at both 65 nm and 45 nm technology nodes. The Wallace tree multiplier dissipated minimum leakage current owing to its structure. In order to reduce the leakage current in each of the multiplier circuits, a heuristic approach is proposed to incorporate hybrid adder modules in the final stage of multiplication that forms the critical delay path and also a high static leakage current zone. Placing Mirror adder and 10 T adders alternatively in the final stage yielded better leakage power characteristics.

Leakage power consumption is an increasingly serious problem in very large-scale integration circuits, especially for portable applications. Two novel approaches to leakage power minimization in static complementary metal-oxide-semiconductor circuits that employ input vector control (IVC) are investigated. The authors model leakage effects by means of pseudo-Boolean functions. These functions are linearized and incorporated into an exact (optimal) integer linear programming (ILP) model, called virtual-gate ILP, which analyzes leakage variation with respect to a circuit's input vectors. A heuristic mixed-integer linear programming (MLP) method is also proposed, which has several advantages: it is faster, its accuracy can be quickly estimated, and tradeoffs between runtime and optimality can easily be made. Furthermore, the MLP model also provides a way to estimate a lower bound on circuit leakage current. The proposed methods are used to generate an extensive set of experimental results on leakage reduction. It is shown that average leakage currents are usually 1.25 times the minimum, confirming the effectiveness of IVC. The heuristic MLP approach is shown to be approximately 13.6 times faster than the exact ILP method, whereas finding input vectors whose power consumption is only a few percent above the optimum. In addition, the lower bound estimated by the MLP model is also within a few percent of the optimal value

There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e5001 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.

Microgrids can provide economic benefits, and those benefits can be maximized through intelligent control. This paper applies a fast and reliable linear programming (LP) approach to the economic dispatch of grid-tied microgrids containing any or all of the following resources: conventional generators, energy storage, demand response resources, and non-dispatchable resources (e.g. solar or wind). The proposed method minimizes the cost to operate the microgrid while meeting various resource constraints. Forecast load and renewable resource power profiles are used to generate linear constraints. Storage conversion losses, which can be much more significant in microgrids, are innovatively accounted for within LP using auxiliary variables. Non-linear constraints on the dispatchable resources are applied by preprocessing the input to LP and post-processing its output.

Leakage power is becoming a dominant contributor to the total power consumption and dual-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> assignment is an efficient technique to decrease leakage power, for which effective design methods have been proposed. However, due to the exponential relation of subthreshold current with process parameters, such as, the effective gate length, oxide thickness and doping concentration, process variations can severely affect both power and timing yields of the designs obtained by those methods. In this paper, we propose a mixed integer linear programming method for dual-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> design that minimizes the leakage power and circuit delay in a statistical sense such that the impact of process variation on the respective yields is minimized. The experimental results show that 30% more leakage power reduction can be achieved by using statistical approach when compared with the deterministic approach

The subthreshold and gate oxide leakage power characteristics of domino logic circuits are evaluated in this paper. The preferred input vectors and node voltage states are identified to minimize the total leakage power consumption in the sleep mode. New low leakage design guidelines based on the results are presented. Previous studies indicate that a discharged dynamic node voltage state with high inputs is preferable to reduce the subthreshold leakage power consumption in an idle dual threshold voltage domino gate. However, the gate oxide leakage is ignored in the previous studies. The significantly increased gate dielectric tunneling current, as described in this paper, shifts the leakage power characteristics of dynamic circuits in the sub-65nm CMOS technologies. Contrary to the previously published techniques in older technologies, a charged dynamic node voltage state with low inputs is preferred for reducing the total leakage power consumption in the wide fan-in dual threshold voltage domino gates. Similarly, a charged dynamic node voltage state with low inputs is preferred for lowering the leakage power consumption in all types of low threshold voltage domino gates in a 45nm CMOS technology

As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is dissipated in the cache hierarchy. To reduce cache leakage, individual cache lines can be kept in drowsy mode, a low voltage, low leakage state. Every cache access may then result in dynamic power consumption and performance penalties. A trade-off between the amount of leakage power saved on one hand, and the impact on dynamic power and performance on the other hand must be reachedTo affect this trade-off, we introduce caches in which the power level of cache lines is controlled with the cache replacement policy. In a slumberous cache, cache lines are maintained at different power save modes which we call levels, which depend on their order of replacement priorities.We evaluate the trade-offs in the context of PLRU, a common cache replacement algorithm. We explore various assignments of the tranquility levels to lines and compare overall power and performance impacts. As technology scales down, the dynamic power required to energize slumberous cache lines drops drastically while the leakage power savings remain roughly steady. The performance penalty--in cycles-- remains constant with technology scaling for each scheme we evaluate.

An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V. >

A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm .

In the previous work, the problem of finding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay, we reduce the number of the LP constraints to be linear in circuit size. For example, the 469-gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the first time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay buffers consumes only 34% peak and 38% average power as compared to an unoptimized design. As shown in previous work, the use of delay buffers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4-bit ALU circuit for which the power consumption was obtained by a circuit-level simulator.

We developed a new post-synthesis algorithm that minimizes leakage power while strictly preserving the delay constraint. A key aspect of the approach is a new threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) assignment algorithm that employs a cost function that is globally aware of the entire circuit. Thresholds are first raised as much as possible subject to the delay constraint. To further reduce leakage, the delay constraint is then iteratively increased by Δ time units, each time enabling additional cells to have their threshold voltages increased. For each of the iterations, near-optimal cell size selection is applied so as to reacquire the original delay target. The leakage power iteratively reduces to a minimum, and then increases as substantial cell upsizing is required to re-establish the original delay target. We show results for benchmark and commercial circuits using a 40nm cell library in which four threshold voltage options are available. We show that the application of the new leakage power minimization algorithm appreciably reduces leakage power after multi-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> synthesis by a leading commercial tool, achieving an average post-synthesis leakage reduction of 37% while also reducing total active area and maintaining the original delay target.

We present a new parallel algorithm for computing a least squares solution to a sparse overdetermined system of linear equations Ax=b such that m×n matrix A is sparse and the graph, G=(V,E), of the matrix \(H = \left[ {\begin{array}{*{20}c}I & {A^T } \\A & O \\\end{array} } \right]\) has an s(m+n)-separator family, that is, either |V| <n0 for a fixed constant n0 or, by deleting a separator subset S of vertices of the size ≤ s(m+n), G can be partitioned into two disconnected subgraphs having vertex sets V1,V2 of the sizes ≤ 2/3 (m+n) and each of the two resulting subgraphs induced by the vertex sets S ∪ Vi, i=1,2, can be recursively s(|S ∪ Vi|)-separated in a similar way. Our algorithm uses O(log (m+n) log2s(m+n)) steps and ≤ s3(m+n) processors; it relies on our recent parallel algorithm for solving sparse linear systems and has several immediate applications of interest, in particular to mathematical programming, to sparse nonsymmetric systems of linear equations, and to the path algebra computations. We most closely examine the impact on the linear programming problem, l.p.p., which requires to maximize cTy subject to ATy ≤ b, y ≥ 0 where A is an m×n matrix. Hereafter it is assumed that m ≥ n. The recent algorithm by N. Karmarkar gives the best known upper estimate (O(m3.5 L) arithmetic operations where L is the input size) for the cost of the solution of this problem in the worst case. We prove an asymptotic improvement of that result in the case where the graph of the associated matrix H has an s(m+n)-separator family; then our algorithm can be implemented using O(m L log m log2s(m+n)) parallel arithmetic steps, s3(m+n) processors and a total of O(m L s3(m+n) log m log2s(m+n)) arithmetic operations. In many cases of practical importance this is a considerable improvement of the known estimates: for example, s(m+n) = √8 (m+n) if G is planar (as occurs in many operations research applications, for instance, in the problem of computing the maximum multicommodity flow with a bounded number of commodities in a network having an s(m+n)-separator family), so that the processor bound is only 8 √8 (m+n)1.5 and the total number of arithmetic steps is O(m2.5L) in that case. Similarly Karmarkar's algorithm and the known algorithms for the solution of overdetermined linear systems are accelerated in the case of dense input matrices via our recent parallel algorithms for the inversion of dense k×k matrices using O(log2k) steps, k3 processors. Combined with a modification of Karmarkar's algorithm, this implies solution of l.p.p. using O(Lm log2m) steps, m2.5 processors. The stated results promise some important practical applications. Theoretically the above processor bounds can be reduced for dense matrix inversion to o(k2.5) and for l.p.p. to o(m2.165) in the dense case and to o(s2.5(m+n)) in the sparse case (preserving the same number of parallel steps); this also decreases the sequential time bound for the l.p.p. by a factor of m0.335, that is, to O(Lm3.165).