ReVIVaL

Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized transistors are used in their design. In this work, by considering on-chip data caches, we study the effect of access latency variations on performance. We discuss performance losses due to the worst-case design, wherein the entire cache operates with the worst-case process variation delay, followed by process variation aware cache designs which work at set-level granularity. We then propose a technique called block rearrangement to minimize performance loss incurred by a process variation aware cache which works at set-level granularity. Using block rearrangement technique, we rearrange the physical locations of cache blocks such that a cache set can have its "n" blocks (assuming a n-way set-associative cache) in multiple rows instead of a single row as in the case of a cache with conventional addressing scheme. By distributing blocks of a cache set over multiple sets, we minimize the number of sets being affected by process variation. We evaluate our technique using SPEC2000 CPU benchmarks and show that our technique achieves significant performance benefits over caches with conventional addressing scheme

Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation. At nanoscale technology nodes, interconnect delay and reliability become the major bottlenecks faced by modern integrated circuits. To resolve these interconnect problems, various emerging technologies, including airgap, nanocarbon, optical, and through-silicon via (TSV), have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to increase the integration density. More importantly, 3D integration and packaging also offer the most promising platform to implement "More-than-Moore" technologies, providing heterogeneous materials and technologies on a single chip. <br />The "Advanced Interconnect and Packaging" Special Issue seeks to showcase research papers on new developments in advanced interconnect and packaging, i.e., on the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies. Additionally, there are two interesting papers on carbon nanotube interconnects and interconnect reliability issues.

In nanoscale technology nodes, process and runtime variations have emerged as the major sources of timing uncertainties which may ultimately result in circuit failure due to timing violation. Therefore, in-field chip health monitoring is essential to track workload-induced variations at runtime in a per-chip basis. There exist a variety of monitoring circuits to track the delay changes of different on-chip components. However, existing techniques either need to stop normal execution of the chip or introduce a significant overhead unless they are carefully placed for very selective locations. Another challenge is to infer the information regarding the health of every critical paths of the chip with limited information obtained by the monitoring system. We address these challenges in this work using a representative path-selection technique based on machine learning. This technique allows us to measure the delay of a small subset of paths and assess the circuit-level impact of workload for a larger pool of reliability-critical paths.

In sub-90 nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated parameters. Variations in the critical process parameters can result in significant fluctuations in the switching speed and leakage power consumption of different transistors in the same chip. In this paper, we study the impact of process variation on issue queues. Due to process variation, issue queues can take variable access latency. In order to work with nonuniform access latency issue queues, by exploiting ready operands of instructions at dispatch time, we propose a process variation aware issue queue design. Experimental results reveal that, for a 64-entry issue queue with half of the entries affected by process variation, our technique recovers most of the lost performance due to process variation and incurs a performance penalty of less than 2% with respect to the performance of issue queues without process variation.

&lt;div class="htmlview paragraph"&gt;In the frame of ESA's Basic Technology Research Programme an integrated Fan-Pump-Separator (FPS) unit, for the European EVA Space Suit System, was developed up to breadboard level. The development was carried out by TECHNOFAN (F) as subcontractor to DORNIER (D) under contract of the European Space Agency.&lt;/div&gt; &lt;div class="htmlview paragraph"&gt;Concept Trade-offs and design definition confirmed the advantages in power, mass and volume of integrating all three functions into a single unit. The unit is driven by one common brushless DC motor. The performance requirements for the three basic functions (oxygen circulation, coolant water circulation and water separation) were derived from the system layout of the life support system for the European EVA Space Suit.&lt;/div&gt; &lt;div class="htmlview paragraph"&gt;The separate functional units were comprehensively tested in preliminary development tests. Final assembly of the functional units led to an integrated breadboard, which was successfully tested.&lt;/div&gt; &lt;div class="htmlview paragraph"&gt;The paper describes the development approach, the concept selection, the design and the tests with their results.&lt;/div&gt;

Malicious modification of integrated circuits (ICs) in untrusted foundry, referred to as “Hardware Trojan”, has emerged as a serious security threat. While side-channel analysis has been reported as an effective approach to detect hardware Trojans, increasing process variations in nanoscale technologies pose a major challenge, since process noise can easily mask the Trojan effect on a measured side-channel parameter, such as supply current. Besides, existing side-channel approaches suffer from reduced Trojan detection sensitivity with increasing design size. In this paper, we propose a novel scalable side-channel approach, named self-referencing, along with associated vector generation algorithm to improve the Hardware Trojan detection sensitivity under large process variations. It compares transient current signature of one region of an IC with that of another, thereby nullifying the effect of process noise by exploiting spatial correlation across regions in terms of process variations. To amplify the Trojan effect on supply current, we propose a region-based vector generation approach, which divides a circuit-under-test (CUT) into several regions and for each region, finds the test vectors which induce maximum activity in that region, while minimizing the activity in other regions. We show that the proposed side-channel approach is scalable with respect to both amount of process variations and design size. The approach is validated with both simulation and measurement results using an FPGA-based test setup for large designs including a 32-bit DLX processor core (~105 transistors). Results shows that our approach can find ultra-small (<0.01% area) Trojans under large process variations of up to ± 20% shift in transistor threshold voltage.

With the ever decreasing transistor feature size in recent years, process variation has become a serious challenge in digital system design, mainly due to the undesirable timing uncertainty it introduces in circuits. This variation in the size of circuit components changes the logic and wire delays that in turn, may result in delay faults or clock degradation. In this paper, we propose to use the emerging approximate computing technique to tackle the process variation problem in new technology points. In this method, functional units (sub-blocks) along critical paths are replaced with a faster approximate version to guarantee timing closure in presence of process variation. Approximation not only applies to critical path sub-blocks but also to the paths with the length close enough to critical path length that variation can potentially increase their delay over the critical path. Evaluation results under several benchmarks show that this method can give a required safety margin against delay faults, while its side-effect, i.e. accuracy loss, is still low and acceptable.

In the past, a variety of approximate functional units have been developed, out of which some approximate functional units can dynamically change the degree of computation accuracy. The more inaccurately they compute, the faster they do. This paper studies high-level synthesis of approximate circuits which efficiently utilizes such accuracy-controllable functional units with variable latency. Under resource and time constraints, our scheduling method tries to minimize the computation error of the output by selectively multicycling operations. In the experiments, we explore the trade-off between performance, hardware cost and accuracy to demonstrate the effectiveness of this work.

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings

Back-end soft and hard defect monitoring using a single test chip

That QoS and Realtime are mutually exclusive is shown by use of simple queuing theory. QoS mechanisms will not be active in the light to moderate (up to 50% average and 80% peak occupancy) communications load regime used by realtime systems, as by definition there is enough communications capacity to satisfy any and all requests in that moderate-load regime. QoS is required only when communications system path occupancy exceeds about 80%, where offered traffic must be forcibly shaped or deferred to fit the insufficient available communications capacity. No realtime system should be designed to operate in that regime, because the resulting large and random-appearing variations in latency make it impossible to achieve realtime behavior, or in many cases, to even achieve stable system operation.

As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior studies have shown that chip operating frequency and leakage power can have large variations due to fluctuations in transistor gate length and sub-threshold voltage. In this work, we study the impact of process variation on microarchitecture soft error robustness, an increasing reliability design challenge in the billion-transistor chip era. We explore two techniques that can effectively mitigate the effect of design parameter variation while significantly enhancing microarchitecture soft error reliability. Our first technique is entry-based. It tolerates the deleterious impact of variable latency techniques on soft error reliability by reducing the quantity and residency cycle of vulnerable bits in the microarchitecture structure at a fine granularity. Our second technique is structure-based. It applies body biasing schemes to dynamically adapt transistor sub-threshold voltage (and hence device-level soft error robustness) to the program reliability characteristics at a coarse granularity. We also combine the two techniques which further produces improved results. Compared to existing process variation tolerant schemes, our proposed techniques achieve optimal trade-offs between reliability, performance, and power. To our knowledge, this paper presents the first study on characterizing and optimizing processor microarchitecture resilience to soft errors in light of process variation.

Harvesting energy from the insulated shield wire with tuning is expected to be a possible solution to the problem of high power supply for online monitoring devices on high-voltage overhead transmission lines. However, the tuning reactor used to harvest energy in insulated ground wire has a small inductance adjustment range, which is difficult to adapt to the fluctuation of equivalent parameters caused by external conditions. In order to improve the load adaptability of the energy harvesting system and the harvested power of the energy harvesting system, this paper studies a magnetic control reactor with self-excited function, which can actively adjust the reactor inductance according to the fluctuation of the equivalent parameters of the energy harvesting circuit. Firstly, based on the multi-conductor system model and the Thevenin theorem, the topological structure and equivalent model of ground wire tuning energy are established. Secondly, taking the energy collection section of 220 kV high-voltage overhead transmission line as an example, the variation range of equivalent parameters is considered when the line is affected by extreme weather conditions such as icing jump and wind deviation, and the body structure of the line is changed, so as to determine the adjustment range of the inductance value of the tuning reactor for reactor parameter design. Finally, the field-circuit coupling transient simulation is carried out by ANSYS Maxwell to obtain the maximum harvested power and the voltage across the reactor under different conditions. The simulation results show that the proposed magnetically controlled reactor can obtain energy as much as possible from the insulated ground wire when the equivalent parameters of the high voltage overhead transmission line and the load change, and effectively limit the voltage within the allowable value of 30 kV insulation level.

As technology scales down, an increasing number of transistors can be integrated into a single chip but process variation becomes more serious. SRAM is one of the key components in a SoC and it occupies a large portion of the SoC. Thus, the SRAM bitcell is typically designed using very small transistors for high integration, which limits the minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCmin</sub> ) of the SoC because of the large threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) mismatch between paired transistors caused by small feature size. As process technology scales down to sub-32nm technology, the 6T SRAM bitcell that is currently used may not achieve proper stability, write-ability, and read-ability at the required operating voltage. In this paper, several approaches are investigated to resolve the issue, such as upsized 6T SRAM bitcell, 8T SRAM bitcell, read- and write-preferred bitcells, and read- and write-assist circuits. HSPICE simulations are performed using PTM 32nm model parameters.

For applications with stringent power budget, such as ultra low power systems and Internet of the things (IoT), power and energy are the most important constraints. It is shown that when the supply voltage is close to the threshold voltage of transistor, known as near threshold computing (NTC), the energy consumption is at its minimum range. However, by reducing the supply voltage not only the circuit performance decreases significantly, but aggravates various reliability mechanisms. Moreover, the performance variation due to process and runtime variation increases exponentially which makes the traditional margining, to address variability, very inefficient. In this paper, we address energy-efficient countermeasures to combat reliability challenges at NTC in order to guarantee resilient and energy-efficient system operation. We propose to partition a functional unit such as Arithmetic Logic Unit (ALU) into multiple smaller and faster functional units and power-gate them whenever they are not used for long time. Simulation results show that by applying the proposed method the energy efficiency of an ALU can be improved by up to 43.4% at NTC with multiple fold reliability improvements due to timing failures.