RTL implementation for a specific ALU of the 32-bit VLIW DSP processor core

Digital signal processing plays an important role in human life nowadays with various applications such as speech recognition, medical imaging, oil prospecting, etc. However, those applications cannot achieve high performance in general-purpose processors due to specific digital signal processing algorithms including Fourier transform, digital filtering, etc. Hence, the emergence of digital signal processors (DSPs) can be considered as urgent and timely solution as the strong optimizations of their architectures aim at maximizing the performance of those applications. In this work, we present a micro-architecture design of the 32-bit VLIW DSP Processor core based on the proposed top-level architecture and instruction set architecture in our previous work. This micro-architecture is then implemented by using the Verilog HDL and simulated in Altera ModelSim tool.

The design and analysis of software which implements digital signal processing (DSP) algorithms on multiprocessor systems is examined. The DSP algorithms that are considered exhibit certain characteristics which are common of DSP algorithms used in communication and control systems. The analysis methods developed use linear complexity algorithms to analyze the software that implements the DSP algorithms. The first step involves finding the repeat factors associated with a basic cycle of the algorithm. Using these repeat factors it is straightforward to (1) find the precedence relationships between tasks and finally a feasible schedule for the multiprocessor, and (2) coordinate and organize the efforts to optimize the software. >

Multiplier-accumulator is a specific hardware unit that performs a common operation - computing the product of two numbers and adding that product to an accumulator. Especially, in digital signal processing applications which consist of a large number of convolution operations, the emergence of MAC unit contributes greatly to the high performance of the systems. This work is about an implementation for a specific MAC unit based on the proposed RISC instruction set architecture (ISA) of 32-bit VLIW Fixed-point DSP processor core presented in our previous work. The computational unit is designed to be flexible for 32-bit/16-bit/8-bit data computations. The implementation is verified to function correctly not only in Modelsim software but also on Altera Cyclone II (2C35) FPGA board.

Validation of Peripheral Pulse Wave Analysis Technique to Detect Aortic Valve State in Continuous-Flow LVADs1

Finite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) applications. Several attempts have been made to develop hardware realization of FIR filters characterized by implementation complexity, precision and high speed. Field Programmable Gate Array is a reconfigurable realization of FIR filters. Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, are now most often realized by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs. In this paper, distributed arithmetic (DA) realization of FIR filter as serial and parallel are discussed in terms of hardware cost and resource utilization.

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas---Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.

Background. Far-Field R-Wave (FFRW) oversensing and P wave blanking are the major causes of inaccurate atrial signal classification in current pacemaker (PM) devices leading to inaccurate stored diagnostic information and to inadequate PM reactions like mode-switching or preventive pacing. The prospective and multi-center MARS (Morphology of Atrial Signals) study therefore investigated during daily life the capabilities of Digital Signal Processing (DSP) in an implanted dual chamber PM to improve P-wave classification accuracy. Methods . 55 patients with an implanted dual chamber PM (Vitatron T- or C-series) were included: During 24 hours with daily life activity and a stress test, a Holter ECG collected surface ECG, PM markers and all atrial EGM’s. The DSP algorithm analysed atrial events sensed nearby a ventricular event using the minimum and the maximum amplitude of the digitalized and filtered signal and the maximum and minimum amplitude of the slope signal. After comparing to the characteristics of a normal P wave, each of these atrial signals were then classified as a true atrial signal or FFRW. DSP classification results were then compared to the conventional PM signal classification by three independent reviewers. Results . Classification accuracy for the traditional PM functionality after optimizing blanking and sensitivity settings was 97.1% (19.5–100%) as compared to 99.4% (76.9–100%) using the DSP algorithm (p<0.001). Conclusion . The DSP algorithm significantly improved the classification accuracy of sensed atrial events as an important prerequisite for a correct diagnostic and therapeutic PM function. The herewith presented approach of analysing atrial signals by form and timing may allow to reduce or even eliminate atrial blanking periods thus leading to larger PM sensing windows to prevent from atrial tachyarrhythmia undersensing without an increase in FFRW sensing.

Context. The digital signal processing is applied in many fields of science, technology and human activity. One of the ways of implementing algorithms of digital signal processing is the development of coprocessors as an integral part of well-known architectures.
 In the case of developing a pipelined device, the presented approach will allow to use software and hardware tools of the appropriate architecture, provide the faster execution of signal processing algorithms, reduce the number of cycles and memory accesses.
 Objective. Objectives are design and characterization study of a pipelined RISC-V processor and coprocessor of digital signal processing which performs fast Fourier transform.
 Method. Analyzing technical literature and existing decisions allow to assess advantages and disadvantages of modern developments and on the basis of which to form the relevance of the selected topic. Model designing and simulation results allow to examine a model efficiency, to determine weak components’ parts and to improve model parameters.
 Results. The pipelined RISC-V processor has been designed which executes a basic set of instructions. Execution time of assembly program on the single-cycled and the pipelined processors have been analyzed. According to the results, the test program on the pipelined processor is executed in 29 cycles, while on the single-cycle processor it takes 60 cycles. The structure of the coprocessor for the fast Fourier transform algorithm and a set of processor instructions that allow working with the coprocessor have been developed. The number of cycles of the coprocessor based on Radix-2 fast Fourier transform algorithm for 512 points is 2358 cycles, and for 1024 points is 5180 cycles.
 Conclusions. Conducted researches and calculations have showed that the application of the developed hardware coprocessor reduces the fast Fourier transform algorithm execution time and the load of the pipelined processor during calculations.

Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign‐precomputation‐based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of Z ‐datapath, and involves precomputation of the direction of rotation for each micro‐rotation angle. The approach involves selecting the optimal micro‐rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro‐rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T‐3FBG676 Kintex‐7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice‐delay product and power‐delay product compared to recent designs. An application of approximate rotation to Hough transform‐based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.

The rapid development of embedded systems brings new opportunities for modernized real-time digital signal processing (DSP) education.This paper introduces a novel real-time DSP laboratory course that aims to give students hands-on experience with real-time embedded systems using Android tablets at an early stage of their careers.The students broaden and deepen their understanding of basic DSP theory and techniques and learn to relate this understanding to real-world observations and applications.The students learn industrially relevant skills such as rapid design prototyping in Python and Android development of DSP applications in C++/Java for computationally constrained mobile devices.The course advances in two phases: structured labs and team projects.In the first half of the course, a series of structured labs are provided to implement and analyze real-time DSP systems that utilize fundamental DSP concepts acquired in the introductory signal processing course.The fundamental concepts include topics such as FIR and IIR filtering, multi-rate processing, sampling, windowing, and spectral analysis.The remaining weeks in the course are about implementing and simulating a DSP algorithm of a student's choice from a set of seminal DSP papers such as adaptive filtering, pitch detection, edge-aware filtering, motion tracking, pattern recognition, etc.The team project revolves around the development, testing, presentation, and documentation to help the students defend their proposed design and receive feedback from the teaching staff.We have offered this course for four years, and the student's feedback in the form of survey questionnaires has confirmed that this course has been successful.

In this paper, we describe the multiple biometric recognition system based on 32 bit floating-point digital signal processor (DSP) and field programmable gates array (FPGA). In addition, it has the function of real-time display, which can help the users easily capture the perfect image that they need. Different from other platforms of using DSP and FPGA, we have two kinds of parallel bus interfaces between them, the EMIF and HPI interface. With the help of the Hardware Description Language (HDL) Verilog HDL, we make it true that the DPS and FPGA can co-process the matching algorithms. Comparing with the matching time that processes only by the DSP, the co-processing is more efficient than the processing only by one processor. Besides, we leave several parallel and series interfaces in our board for the future use. Therefore, our system can be applied to many different digital signal processing domains and provide them an excellent computing platform.

The requirement for efficient digital signal processing (DSP) systems and its solutions increases highly over the last few years. DSP techniques as well as its algorithms are necessary for day to day life tool namely smartphone, set-top unit (STU), video and acoustic players, digital cameras, digital television, etc. This paper describes a comparative study on knowledge-based digital filter structure namely transposed form, direct form, and systolic array. To implement the parallel processing the systolic array structure is often used. A Goertzel algorithm is implemented in the field-programmable gate array (FPGA) Altera EP4CE115F29C7 device which is used to determine the discrete Fourier transform (DFT). Finally, filtering technique is implemented efficiently by dividing filter coefficients and data into odd and even which increases the computational speed. The computational speed and functional verification results are achieved by using MATLAB. The Altera DSP builder and Simulink are used for the implementation of Goertzel algorithm. The 64-tap systolic low-pass filter structures offer 213.97-μs-less delay than the transposed form, 1700 μs, and direct form, 3900 μs, structures. Similarly for 2048-tap low-pass filter using sub-filter offers 49.397-ms computational speed and direct filtering offers 53.257 ms.

In this article, we review our recent research progresses on the field programmable gate array (FPGA)-based real-time generation and reception of orthogonal frequency-division multiplexing (OFDM) signals for the short-reach direct-detection system and radio-over-fiber (RoF) system. With the low-complexity real-time digital signal processing (DSP) algorithms, a high-definition video signal with a data rate of 2.97 Gb/s transmission over 20 km single-mode fiber (SMF) without using forward error correction (FEC) technique is experimentally demonstrated in an intensity-modulated direct-detection optical OFDM system in the presence of sampling frequency offset (SFO). In addition, a real-time X-band OFDM-RoF system with heterodyne detection was also realized. With the help of Reed-Solomon coding with a multiplesymbol interleaving/de-interleaving scheme, the 16-ary quadrature amplitude modulation (16-QAM) OFDM-RoF signals over 10-m wireless and 2.26-km SMF-28 link was successfully achieved with a post-FEC bit error rate less than 1×10-9.

Assigning service requests in Voice-over-Internet gateway multiprocessors

Digital signal processing (DSP) has been widely applied in optical communication systems to mitigate various signal distortions and has become one of the key technologies that have sustained data traffic growth over the past decade. However, the strict energy budget of application-specific integrated circuit-based DSP chips has prevented the deployment of some powerful but computationally costly DSP algorithms in real applications. As a result, fiber nonlinearity-induced signal distortions impede fiber communication systems, especially in wavelength-division multiplexed (WDM) transmission systems. To solve these challenges in DSP, there has been a surge of interest in implementing neural networks-based signal processing using photonics hardware (i.e., photonic neural networks). Photonic neural networks promise to break performance limitations in electronics and gain advantages in bandwidth, latency, and power consumption in solving intellectual tasks that are unreachable by conventional digital electronic platforms. This work proposes a photonic recurrent neural network (RNN) capable of simultaneously resolving dispersion and both intra and inter-channel fiber nonlinearities in multiple WDM channels in the photonic domain, for the first time to our best knowledge. Furthermore, our photonic RNN can directly process optical WDM signals in the photonic domain, avoiding prohibitive energy consumption and speed overhead in analog to digital converters (ADCs). Our proposed photonic RNN is fully compatible with mature silicon photonic fabrications. We demonstrate in simulation that our photonic RNN can process multiple WDM channels simultaneously and achieve a reduced bit error rate compared to typical DSP algorithms for all WDM channels in a pulse-amplitude modulation 4-level (PAM4) transmission system, thanks to its unique capability to address inter-channel fiber nonlinearities. In addition to signal quality performance, the proposed system also promises to significantly reduce the power consumption and the latency compared to the state-of-the-art DSP chips, according to our power and latency analysis.