S Parameters Optimization of High-Speed Differential Vias Model on A Multilayer PCB

The signal integrity of the circuit, as one of the important design issues in high-speed digital system, is usually seriously affected by the signal reflection due to impedance mismatch in the DDR3 bus. In this paper, a novel optimization method is proposed to optimize impedance mismatch and reduce the signal refection. Specifically, by applying the via parasitic, an equivalent model of DDR3 high-speed signal transmission, which bases on the match between the on-die-termination (ODT) value of DDR3 and the characteristic impedance of the transmission line, is established. Additionally, an improved particle swarm optimization algorithm with adaptive perturbation is presented to solve the impedance mismatch problem (IPSO-IMp) based on the above model. The algorithm dynamically judges particles' state and introduces perturbation strategy for local aggregation, from which the local optimum is avoided and the ability of optimization-searching is activated. IPSO-IMp achieves higher accuracy than the standard algorithm, and the speed increases nearly 33% as well. Finally, the simulation results verify that the solution obviously decreases the signal reflection, with the signal transmission quality increasing by 1.3 dB compared with the existing method.

Via design is an important factor for signal integrity. Usually there are lots of ground vias on the PCB board at high frequencies. Transmission lines need to turn or change layer, which invariably leads to impedance discontinuity and also result in the disconnection of the signal return path. To reduce the area surrounded by the signal return path and to diminish electromagnetic radiation, ground vias are added to provide the shortest return path signal. To research the influence on the transmission parameters brought by ground vias, considerable simulation work was performed and via optimization based on the simulation results was undertaken. By adjusting the gap between ground via and edge of transmission lines and the density of the vias, parameters for high speed signals transmission lines were optimized. The relations between transmission parameters and ground via placement are plot in this paper. Moreover, for incoherent signal transmission differential pair, the gap between differential lines is not identical throughout the trace, which leads to the weak signal transmission quality at high frequency due to the non-identical coupled capacitance between the lines. Placing several ground vias at the turning and side of differential transmission lines, signal integrity is enhanced in simulation results.

This paper describes the two key aspects of via transition optimization methodology: impedance matching and power plane resonance suppression. Ground vias are used to improve the impedance mismatch caused by the via transition and the optimal location of the ground vias at the same time helps to suppress the resonance caused by the cavity effect of the power plane pair. Full-wave electromagnetic simulations were carried out to demonstrate that via transition optimization is able achieve resonance-free high bandwidth operation. Optimal use of ground vias will not only enhance impedance matching but also significantly suppress suppression due to power plane resonance. Test vehicle characterizations were also carried out to demonstrate the impact of ground vias and power plane resonance characteristics on signal integrity.

In high-speed systems, large switching current drawn from power supply seriously degrades the system performance. This paper discloses a signal integrity (SI) issue related to power integrity (PI). A high-speed memory subsystem is used to evaluate the impact of switching current on SI using eye diagrams. Several test cases are studied to clarify the signal susceptibility from the voltage variation of power due to switching current. Full-wave and circuit simulations are used to validate the hypothesis of noise immunity.

In high-speed digital systems containing dense digital devices, such as microcontrollers, microprocessors, graphic processors, network processors, switching hubs, field-programmable gate arrays, and application-specific integrated circuits (ICs), the interconnects are no longer transparent. This has been the case for systems since clock frequencies rose above 50 MHz, which includes just about all digital products used today. Unless special care is taken in their design and implementation, a high-speed system will fail due to one or more problems generally grouped into the families of signal integrity (SI), power integrity (PI), or electromagnetic interference (EMI) <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> .

The ground vias are used to interconnect the different ground planes existing in a package structure, but also to prevent the propagation of parasitic modes like the parallel-plate mode inside the structure. From a signal integrity perspective, these parasitic modes degrade and limit the performance of a package since they introduce undesired resonances in the electrical response of the structure. Thus, the distribution of the ground vias is of great importance in the design of advanced packages. Using full-wave simulators, we have observed the distribution of the electric and magnetic fields as a high-frequency signal propagates through vertical transitions surrounded by ground vias. The information from the distribution of fields and the corresponding S-parameters were obtained from simulations for different configurations of ground vias in a vertical transition; these are the bases of the paper. The purpose of the presented analysis is to understand the relationship between the frequency at which the resonances associated with the propagation of parasitic modes occur and the configuration of the ground vias.

This paper studies the distribution of via return currents in printed circuit boards and packages. Generally, each return current splits into a conduction current through the ground vias of the structure and a displacement current between the reference planes. An analytical method for the calculation of both conduction and displacement current is described together with an equivalent circuit. The application of the calculation method to simple test structures illustrates the fundamental behavior of the return current. In certain frequency ranges, the magnitude of the displacement current in the return path can become considerably larger than the original signal current. The increase of the displacement current is of interest since it may cause e.g. signal integrity problems.

The rapid development of information and communication technologies has driven the rapid growth of data traffic and the large requirement of high-speed optical transceiver modules. Usually, optical subassemblies through flexible printed circuit boards (PCBs) connect with the hard PCBs to compose as optical transceiver modules. Because of the impedance mismatch of connection between flexible PCB and hard PCB, the operation bandwidth of the module can be limited. In this paper, the design of connection between flexible PCB and hard PCB in optical subassembly modules will be investigated for increasing the operation speed of the module. First, the transmission bandwidth of flexible PCB is analyzed. High-frequency performances of three transmission line structures, micro-strip line, grounded coplanar waveguide, and top ground micro-strip line, are investigated in flexible PCB. High-frequency performances of flexible PCB with different bending types are also investigated. The flexible PCB has been verified to be suitable to use in 25 Gb/s applications. Next, the high-speed transmission performance is analyzed through the connection between flexible PCB and hard PCB, because the impedance mismatch usually occurs at the connection. The ground pads are added near the signal line of flexible PCB, and the ground pads are connected to the ground layer in PCB through ground vias. The anti-pad in hard PCB is added under the signal solder pad. The dip of S21 response can be eliminated by the optimized ground pad. The impedance mismatch can be reduced by the optimized anti-pad, the impedance increases from 40-Ω to 49-Ω at the connection between flexible PCB and hard PCB, and the transmission bandwidth can increase from 16.5 GHz to 23.5 GHz. TO-46 header is a common and low-cost packaging solution for DFB laser and photodiodes. The connection between flexible PCB and TO-46 header is also investigated. While the connection has a gap, the dip of frequency response will occur at lower frequency. While the connection is very close, the bandwidth can be larger than 25 GHz. The flexible PCB, hard PCB, and TO-46 header are combined together, and the 23 GHz transmission bandwidth can be obtained. The 25 Gb/s transmission eye diagram is also measured, and the eye height, rise time, fall time, and Q-factor are 268.14 mV, 13.78 ps, 13.56 ps, and 8.76, respectively. The combined flexible PCB, hard PCB, and TO-46 header are verified to be suitable to apply in 25 Gb/s optical subassembly modules, and will be able to be used in 100G Ethernet.

Multi-gigabit serial channel design has become more and more important since channel margins are becoming tighter as operating frequencies increase. Most engineers working on these channels have been plagued by several different types of signal integrity problems including impedance discontinuities, reflections, attenuation, undershoot and overshoot, and crosstalk. In reality, many signal integrity problems are caused by impedance discontinuities. These discontinuities can be caused by physical discontinuities, system parasitics, or design mistakes. We need to understand these discontinuity issues to improve full channel from package to PCB board. When most designers simulate a channel, they concatenate separate package and PCB models. Using these concatenated models they simulate the data path in a channel simulation test bench. This piecewise or concatenated channel model is incomplete because it does not carefully consider the interface between the BGA package and the PCB. The hidden factor which makes the concatenated channel model differ from real channel measurement will be disclosed in this paper. A more detailed solder ball analysis has also been done during this process. We learn from the above results that if the package is soldered down to the PCB and measured together, additional loss occurs due to the package to board transition. The combined channel is more capacitive than the concatenated channel in the package to board transition region. The excess capacitance due to BGA solder ball transition is due to the physics of the interface and can not be easily eliminated. It is shown that system performance degradation is very sensitive to the impedance discontinuity introduced at the BGA/PCB interface. This paper will introduce a spiral via structure which is shown to be a more effective way to compensate the transition discontinuity seen at the BGA/PCB interface. This paper also shows how the spiral via structure was implemented and optimized in the BGA package. The overall channel performance improvement by using spiral via structures in BGA package is proven by the simulation and measurement.

One of the major drawbacks of current teleradiology systems is the relatively low data transmission rate of modem-based systems, resulting in image transmission times of several minutes up to hours for entire CT or MR examinations. Video image transmissions, on the other hand, result in significant quality reduction and loss of diagnostically relevant information. The objective for our teleradiology project therefore was to establish a high-speed digital image transfer system that would allow interactive sessions for discussing even large image series without loss of information.

Digital application has moved towards operating speed of hundreds of Mega Hertz, with the sampling speed of ADC moving into Giga Hertz range. There is an increasing need for the design and development of a high-speed data acquisition system that is capable of capturing and processing digitized analogue signal at high speed. Due to the tight timing budget, high operating speed components, Emitter-Coupled-Logic families components with rise time of typically less than 300 ps were used in the design. With this operating speed and short rise time, signal integrity issues like reflections due to impedance mismatches and crosstalk among the traces of the printed circuit board can no longer be neglected. A quick and reliable approach was taken in the design and implementation of a 1 GHz high-speed data acquisition system using commercial-off-the-shelf discrete components. High-speed digital design issues and methodology were explored in this project and verified with the implemented hardware. This paper gives an overview of the system and focuses on the use of functional and signal- integrity computer simulation software to confirm system performance at the early design stage before actual hardware implementation. Simulation results were further confirmed with the actual hardware implemented, and was found to be close. This has helped to reduce the design cycle time and development cost of the project.

A novel method is developed to reconstruct the physically structures of a nonuniform couple transmission lines from layer peeling algorithm and genetic algorithm. Base on the time domain reflection (TDR) measurement, the impedance profile of the device under test (D.U.T) is first derived by layer peeling transmission line synthesis. Then, the genetic algorithm (G.A.) is employed to extract the parameter of the lumped/distributed circuits in high-speed digital circuit. As a result, the system characteristic can be easily obtained by the extracted model and SPICE circuit simulation software.

Switching noise-induced voltage fluctuation might result in a serious timing skew or false triggering in a high-speed digital system. We propose a new approach called external coupled resistive termination (ECRT) for suppressing this noise. Analyzing the resonant field patterns reveals that the bulk noise is accumulated close to the plane edges because of the open-end boundary condition. Thus, adding extra loading at the field bulk effectively reduces the quality factors and consequently minimizes the noise accumulation. A Y-shaped power distribution network was studied with a frequency controllable input-output (I/O) buffer model. Simulation results indicate that the noise level is significantly suppressed. The optimal noise reduction rate is 80% at resonance with an overall reduction rate of 50%. Scattered placement of the ECRT was also investigated and the corresponding noise reduction rate was 50%. Reasons for that will be discussed.

In modern digital systems, most of electromagnetic radiated emission originates from high-speed digital clock signal. In order to reduce the electromagnetic radiated emission from the clock signal, spread spectrum clock had been used. It had been conventionally realized by modulating the period of a regular clock, using a phase locked loop (PLL) or a delay locked loop (DLL). However, neither of them can be implemented with simple circuit. To overcome this, suppressed carrier clock (SCC) has been recently proposed, which is implemented by intentionally skipping transitions of a regular clock. In this paper, we analyze the effects of modulation profile on the suppression of electromagnetic radiated emission. Numerical simulation results show that saw-tooth modulation is an optimal method in terms of performance and feasibility. We also propose a simple circuit for modulation and demodulation of the SCC with the saw-tooth modulation profile. Finally, we implemented the proposed circuit on an ALTERA chip, and it achieves 6 dB suppression of electromagnetic radiated emission.

Advances in interconnect technologies, such as the increase of the number of metal layers and 3-D stacking technique, have paved the way for higher functionality and superior performance while reducing size, power, and cost in today's integrated circuits and package products. With the increase of clock frequency and edge rates as well as the continuously downscaling of feature size and 3-D interconnect technologies in high-speed systems, signal integrity (SI) effects such as signal delay, reflection, attenuation, dispersion and crosstalk have become one of the dominant factors in current deep sub-micrometer CMOS technologies limiting overall performance of high-speed systems.Another major difficulty is the power integrity (PI) issue. For example, IR drop is caused by the finite resistivity (R) of metals and current (I) drawn off from the power/ground planes. Chip designs are susceptible to IR drop, especially when the integrated circuit (IC) supply voltage Vdd decreases with the scaling of silicon processes. IR drop is proportional to the resistance of the power/ground plane. When the resistance of power/ground plane increases, with the shrinking of complex geometries, the IR drops will in turn increase as well. To further confound the difficult issue, the rise of the thermal temperature due to the current carrying interconnects also has tremendous impact on the IC performance and reliability. Current flow in a VLSI interconnect can cause a power dissipation, which is referred to as Joule heating or self-heating. The Joule heating effects are becoming increasingly significant with the shrinking scale of silicon process because of the increase of on-chip power density, inclusion of more metal layers with higher densities, and the use of dielectric materials with lower thermal conductivities. Subsequently, the temperature effects on the electrical performance of 3D systems should be carefully considered as well in the electrical designs.Unfortunately, almost all practical SI and PI problems are multi-physics in nature, and various physical phenomena are usually interacting and coupling to each other. For instance, the resistivity of most conducting metals increases linearly with the increases of the surrounding temperature resulting from the Joule heating by electric currents flowing through the conductors. Therefore, in order to accurately characterize the performance of high power integrated circuits (ICs), packages and printed circuit boards (PCBs), it is essential to account for both electric and thermal effects and the intimate couplings between them.In this paper, we propose to use non-conformal, non-overlapping domain decomposition methods (DDMs) for the signal integrity analyses and thermal-aware DC IR drop co-analysis of high-power IC-Package-PCBs. The proposed DDM starts by partitioning the composite device into inhomogeneous sub-regions with temperature dependent material properties. Subsequently, each sub-domain is meshed independently according to its own characteristic features. As a result, the troublesome mesh generation task for complex ICs can be greatly subdued. Moreover, the proposed thermal-aware DC IR drop co-analysis applies the non-conformal DDMs for both conduction and steady state heat transfer analyses with a two-way coupling between them. Furthermore, we extend the non-conformal DDM to study transient thermal temperature distribution within complex ICs. Numerical examples, including an IC package and an IC-Package-PCB, demonstrate the flexibility and potentials of the proposed non-conformal DDMs for SI analyses and thermal-aware DC IR-drop co-analysis.