Satisfiability Attack-Resistant Camouflaged Two-Dimensional Heterostructure Devices.

CAD and CAE model update on manufactured shapes is a key process in the industry 4.0, where design, manufacturing and maintenance are integrated elements. Digital Twin models, together with Reverse Engineering (RE) techniques, allow tracking components performances during production and verifying the compliance with design requirements during the component lifetime. The need to have RE processes with a small impact on the production is driving the development of these models towards numerical techniques with fast computing performances. In this context, morphing techniques, largely deployed in the field of CAE models update, represent a valuable alternative to conventional RE techniques, because of their reduced computational time and capability to preserve the initial topology of the model. In the work presented in this paper, Radial Basis Function morphing technique has been used for the update of ITER Winding Pack CAD model on scan data acquired from the manufactured component.

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

In this chapter, we present methodologies and technologies for automating reverse engineering (RE) through digital imaging and computer vision. We begin this chapter with a definition of RE in terms of generating computer-aided design (CAD) models from existing objects and components. We use the term computer-aided reverse engineering (CARE) to describe this process. With this definition, we present a brief overview of the traditional approach to RE using coordinate measuring machines (CMMs). Then, we begin the main focus of the chapter where we explore digital imaging and computer vision as an alternative to CMMs. This exploration begins with data acquisition, where we present laser-based range scanners as a promising approach. For these scanners, we explain and highlight differences in data resolution and scanning rates and contrast those to CMM performance. Next, we present a processing pipeline for creating CAD models using these scanners. This processing includes tasks such as view registration, surface integration, patch reconstruction, model fitting, noise removal, and other functions. This chapter explains these topics to help the reader understand their importance in designing an RE imaging system and the impact that various parameters have on modeling accuracy.

High-quality Si nanowire field effect transistors (FETs) were fabricated using thermal nanoimprint and chemical wet etching technologies. FET structures of different lengths demonstrate high carrier mobility with values of about 750 cm2/Vs and low volume densities of active traps in the dielectric layers of 5 × 1017 cm−3 eV−1. We investigated the transport properties of these n-type channel structures using low-frequency noise spectroscopy before and after gamma radiation treatment. Before gamma irradiation, FET structures with lengths of less than 4 μm exhibited noise from contact regions with 1/(L2) dependence for the relative 1/f noise. After gamma radiation, the spectra reflected the priority of channel noise with 1/L dependence for all samples. The transport characteristics show that the fabricated nanowire FETs improved scalability, decreased parameter scattering, and increased stability after treatment. The results demonstrate that these nanowire FETs are promising for nanoelectronic and biosensor applications due to the cost-efficient technology and advanced performance of FETs with improved stability and reliability.

The sustained advancement in semiconducting core-shell nanowire technology has unlocked a tantalizing route for making next generation field effect transistor (FET). Understanding how to control carrier mobility of these nanowire channels by applying a gate field is the key to developing a high performance FET. Herein, we have identified the switching mechanism responsible for the superior performance of a Si-Ge core-shell nanowire quantum dot FET over its homogeneous Si counterpart. A quantum transport approach is used to investigate the gate-field modulated switching behavior in electronic current for ultranarrow Si and Si-Ge core-shell nanowire quantum dot FETs. Our calculations reveal that for the ON state, the gate-field induced transverse localization of the wave function restricts the carrier transport to the outer (shell) layer with the pz orbitals providing the pathway for tunneling of electrons in the channels. The higher ON state current in the Si-Ge core-shell nanowire FET is attributed to the pz orbitals that are distributed over the entire channel; in the case of Si nanowire, the participating pz orbital is restricted to a few Si atoms in the channel resulting in a smaller tunneling current. Within the gate bias range considered here, the transconductance is found to be substantially higher in the case of a Si-Ge core-shell nanowire FET than in a Si nanowire FET, which suggests a much higher mobility in the Si-Ge nanowire device.

In this paper we show that oxide-coating of Si nanowires (NWs) limit the response of Si NW field effect transistors (FETs) to their environment, also if the NWs are coated with adsorptive molecular functionality. This behavior is in accord with prior works showing that Si/SiO2 interface trap and scatters carriers and compensate for the back gate voltage of FETs. Etching-away the SiO2 and terminating the surface of Si NWs by molecular functionality through stable Si-C bond lead for high-sensitive detection levels of various polar and a-polar vapor compounds at concentration levels down to few tens of ppb. Using an array of molecule-terminated, oxide-free Si NW FETs in an electronic nose configuration allow analysis of complex multi-component (bio) chemical media and good discrimination between simulated patterns of ldquohealthyrdquo and ldquocancerousrdquo breathe.

We present results of a comprehensive study of the liquid-back gate coupling effect in our Si nanowire (NW) field-effect transistor (FET) structures using noise spectroscopy in different operation modes, including variable back-gate voltage. The constant channel resistance regime was used for measurements of the transport and noise properties of the liquid-gated Si NW FETs and simulations using Sentaurus TCAD software to improve our understanding of the coupling effect phenomena. The concentration profiles were simulated for different liquid- and back-gate voltages, which correspond to the experimental working points. The noise spectra were studied while tuning the position of the conducting channel in the liquid-gated Si NW FET. Results demonstrate that the dominant flicker noise mechanism in such structures is the number fluctuations due to the localization of the conducting channel near the dielectric layer of the liquid gate.

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. Obfuscation has emerged as a promising approach to ensure supply chain security by countering the reverse engineering (RE) based attacks on integrated circuits. However, the state-of-the-art obfuscation methods use key gates or camouflage existing gates which incur large design overhead and high cost of RE. In this paper, we propose a new obfuscation method based on don't care primitives that not only modifies the sub-circuit functionality but also can be implemented during design process at the cost of little area and delay overhead. Most of the existing obfuscation techniques focus on hiding layout information from circuit attackers, our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult and to increase the RE complexity while fulfilling overall circuit specifications. An analysis of RE complexity is provided by functionally obfuscating ISCAS-85 Benchmarks. Our experimental results clearly indicate that significant RE complexity can be achieved at minimal design overhead (average area overhead is 5.436% and average delay overhead is about 7.473%).

A junctionless field-effect transistor (FET) has been proposed using a Si nanowire FET. It avoids the junction formation process and shows less sensitivity to the channel interface. We discuss the junctionless FET on a Ge-on-insulator substrate, which combines the higher mobility in Ge than in Si with all the advantages of a junctionless FET. The device shows similar current–voltage (I–V) characteristics to conventional FETs, and the on/off current (Ion/Ioff) ratio is larger than 104. The field-effect mobility seems to be rather flat with regard to the carrier density.

In this paper, we evaulated the shape and size effects of Si and Ge nanowire (NW) field-effect transistors (FETs) on device performance using sp3d5s* tight-binding (TB) model and semi-classical top-of-barrier ballistic transport model. Our simulation results show that smaller cross-sectional area is desirable for high frequency device applications and for larger ON-state currents, square cross-section may be desirable due to larger cross-sectional area and insulator capacitance. Furthermore, it is also observed that due to quantum effects, the gate capacitance to gate oxide capacitance (Cg/Cox) ratio for the small size NW FETs could be much less than one, rendering the classical assumptions and calculations invalid for nano scale FETs. In this sub-nano region, therefore, a new set of assumptions and calculations in terms of effective mass, bandgap, and one-dimensional density-of-states should be implemented as quantum effects start to play an important role in device performance.

During the last few decades, the microelectronics industry has actively been investigating the potential for the functional integration of semiconductor-based devices beyond digital logic and memory, which includes RF and analog circuits, biochips, and sensors, on the same chip. In the case of gas sensor integration, it is necessary that future devices can be manufactured using a fabrication technology which is also compatible with the processes applied to digital logic transistors. This will likely involve adopting the mature complementary metal oxide semiconductor (CMOS) fabrication technique or a technique which is compatible with CMOS due to the inherent low costs, scalability, and potential for mass production that this technology provides. While chemiresistive semiconductor metal oxide (SMO) gas sensors have been the principal semiconductor-based gas sensor technology investigated in the past, resulting in their eventual commercialization, they need high-temperature operation to provide sufficient energies for the surface chemical reactions essential for the molecular detection of gases in the ambient. Therefore, the integration of a microheater in a MEMS structure is a requirement, which can be quite complex. This is, therefore, undesirable and room temperature, or at least near-room temperature, solutions are readily being investigated and sought after. Room-temperature SMO operation has been achieved using UV illumination, but this further complicates CMOS integration. Recent studies suggest that two-dimensional (2D) materials may offer a solution to this problem since they have a high likelihood for integration with sophisticated CMOS fabrication while also providing a high sensitivity towards a plethora of gases of interest, even at room temperature. This review discusses many types of promising 2D materials which show high potential for integration as channel materials for digital logic field effect transistors (FETs) as well as chemiresistive and FET-based sensing films, due to the presence of a sufficiently wide band gap. This excludes graphene from this review, while recent achievements in gas sensing with graphene oxide, reduced graphene oxide, transition metal dichalcogenides (TMDs), phosphorene, and MXenes are examined.

We present Ares, a reverse engineering technique for assisting in the analysis of data recovered for the investigation of mobile and embedded systems. The focus of investigations into insider activity is most often on the data stored on the insider's computers and digital device - call logs, email messaging, calendar entries, text messages, and browser history - rather than on the status of the system's security. Ares is novel in that it uses a data-driven approach that incorporates natural language processing techniques to infer the layout of input data that has been created according to some unknown specification. While some other reverse engineering techniques based on instrumentation of executables offer high accuracy, they are hard to apply to proprietary phone architectures. We evaluated the effectiveness of Ares on call logs and contact lists from ten used Nokia cell phones. We created a rule set by manually reverse engineering a single Nokia phone. Without modification to that grammar, Ares parsed most phones' data with 90% of the accuracy of a commercial forensics tool based on manual reverse engineering, and all phones with at least 50% accuracy even though the endianess for one phone changed.

In the reverse engineering area, while the reconstruction of surfaces from scanned or digitised data has been developed, a geometric model of an existing object is often unavailable. This paper presents a new approach to the reconstruction of a surface. The proposed methodology finds the basic parts of the surface and blends surfaces between them. Each basic geometric part is divided into triangular patches which are compared using normal vectors for face grouping. Each group is categorised into analytical surfaces such as a part of a cylinder, a sphere or a cone, and plane shapes to represent the basic geometric surface. Each basic geometric surface is then implemented to the infinitive surface (unbounded plane, cylinder, cone, or sphere: cylinder, cone, and sphere are full shapes of analytical surfaces). The infinitive surface's intersections are trimmed by boundary representation model reconstruction. The proposed methodology has several advantages such as computational efficiency and automatic functional modelling in reverse engineering. Reverse engineering should be the 3D equipment of the photocopying process.

Due to the trend of globalized semiconductor supply chain, integrated circuits (IC) and hardware intellectual property (IP) are prone to serious security threats such as reverse engineering and IP piracy. In addition to the post-fabrication authentication techniques (e.g., IP metering), various hardware hardening approaches have emerged to resist reverse engineering and IP piracy. This chapter reviews three representable security hardening approaches—camouflaging, logic encryption/locking, and design obfuscation—that are applied to ICs at layout, gate, and register transfer levels. Particularly, this chapter presents a dynamic state-deflection-based obfuscation method, which deflects the state transition from the original transition path to a black hole cluster if an invalid key is applied to the hardware IP. This obfuscation method can successfully thwart the reverse engineering attack that exploits the code analysis support from electronic design automation (EDA) tools. Furthermore, this chapter extends the idea of design obfuscation for two-dimensional IC to emerging three-dimensional (3D) IC design technology. The proposed method is based on the insertion of a Network-on-Chip (NoC)-based shielding plane between two commercial dies to build the secure 3D ICs without involvement of trustworthy foundries.

Models and transformations are the primary elements of Model Driven Architecture (MDA). On the other hand, Reverse Engineering (RE) also deals with the intermediate models and different transformation practices to produce the desired output models. Consequently, MDA have been utilized in the field of reverse engineering. This article inspects and summarizes the applications of MDA for RE. Particularly, a Systematic Literature Review (SLR) is performed to analyze 23 studies published during 2006-2017. Consequently, five leading RE techniques are identified. Moreover, 10 tools regarding MDA-based reversed engineering have been presented. Furthermore, modeling and transformation approaches are investigated for reverse engineering. The results of this SLR are highly valuable for academia and industry professionals of the domain.