SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

Switch Allocation (SA) carries a critical pipeline stage in improving latency in Network-on-Chip (NoC). SA is responsible for assigning flits at the input queue to the output port for sending them to their destination. The allocation specifies the matching between the arriving requests and assigning ports to them. To maximize this matching, a Virtual Channel (VC) router architecture is suggested in this paper. The proposed design enhances the chances of mapping for the packets appearing in SA stage. The proposed architecture is evaluated using cycle accurate tool Booksim. The latency results indicate significant performance improvement of NoC router.

The present contribution explores the design space for virtual channel (VC) and switch allocators in network-on-chip (NoC) routers. Based on detailed RTL-level implementations, we evaluate representative allocator architectures in terms of matching quality, delay, area and power and investigate the sensitivity of these properties to key network parameters. We introduce a scheme for sparse VC allocation that limits transitions between groups of VCs based on the function they perform, and reduces the VC allocator's delay, area and power by up to 41%, 90% and 83%, respectively. Furthermore, we propose a pessimistic mechanism for speculative switch allocation that reduces switch allocator delay by up to 23% compared to a conventional implementation without increasing the router's zero-load latency. Finally, we quantify the effects of the various design choices discussed in the paper on overall network performance by presenting simulation results for two exemplary 64-node NoC topologies.

Network-on-Chip (NoC) is a popular communication and interconnection structure for multi or many-core system-on-chip (SoC). It mainly consists of routers, network interfaces and communication links. It typically utilizes virtual channels (VCs) to improve wormhole routing among the SoC cores by enabling multiple packet flits to share NoC communication links. DAMQ (Dynamically Allocation Multi Queues) based VC organization has higher buffer utilization but it also has a few problems. We present a novel NoC router architecture that provides solutions to these problems. It utilizes dynamic VC based buffering and index based arbitration methodologies. Arbitration is a critical operation employed in NoC routers that may results in lower speed, weak fairness, and difficulties in pipelining. Our arbitration techniques used in the presented router architecture overcome these problems. We have simulated and implemented our 2D-mesh NoC router using System-Verilog. The experimental results confirm the efficiency of our proposed NoC router in terms of superior router power and ASIC area as well as its operating speed. Performance metrics for different NoC configurations are determined and evaluated for a variety of traffic patterns.

Technology scaling has led to the integration of many cores into a single chip. As a result, on-chip interconnection networks start to play a more and more important role in determining the performance and power of the entire chip. Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multi-core processors. However the virtual-channel (VC) buffers in the NoC consume significant dynamic and leakage power of the system. To improve the energy efficiency of the router design, it is advantageous to use small buffer sizes while still maintaining throughput of the network. This paper proposes two new virtual channel allocation (VA) mechanisms, termed Fixed VC Assignment with Dynamic VC Allocation (FVADA) and Adjustable VC Assignment with Dynamic VC Allocation (AVADA). The idea is that VCs are assigned based on the designated output port of a packet to reduce the Head-of-Line (HoL) blocking. Also, the number of VCs allocated for each output port can be adjusted dynamically. Unlike previous buffer-pool based designs, we only use a small number of VCs to keep the arbitration latency low. Simulation results show that FVADA and AVADA can improve the network throughput by 41% on average, compared to a baseline design with the same buffer size. AVADA can still outperform the baseline even when our buffer size is halved. Moreover, we are able to achieve comparable or better throughput than a previous dynamic VC allocator while reducing its critical path delay by 60%. Our results prove that the proposed VA mechanisms are suitable for low-power, high-throughput, and high-frequency on-chip network designs.

With the trend to integrate a large number of cores on a single chip, Network-on-Chips (NoCs) are becoming more important for communication on System-on-Chips (SoCs). Designing high throughput and low latency on-chip networks with reasonable area overhead is one of the main technical challenges. This paper proposes an architecture of router with on-the-fly virtual channel (VC) allocation for high performance on-chip networks. By performing the VC allocation during the time a packet is traversing the crossbar switch, the pipeline of a packet transfer can be shortened in a non-speculative fashion without the penalty of area. The proposed architecture has been implemented on FPGA and evaluated in terms of network latency, throughput and area overhead. The experimental results show that, the proposed router with on-the-fly VC allocation can reduce the network latency by 40.9%, and improve throughput by 47.6% as compared to the conventional VC router. In comparison with the look-ahead speculative router, it improves the throughput by 8.8% with 16.7% reduction of area for control logic.

A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <2% degradation in throughput. The implementation overhead of TVA is negligible.

Designing high throughput and low latency on-chip networks with reasonable area overhead is becoming a major technical challenge. This paper proposes an architecture of router with on-the-fly virtual channel (VC) allocation for high performance on-chip networks. By performing the VC allocation based on the result of switch allocation, the dependency between the VC allocation and switch traversal is removed and these stages can be concurrently performed in a non-speculative fashion. In this manner, the pipeline of a packet transfer can be shortened without the penalty of area. The proposed architecture has been implemented on FPGA and evaluated in terms of network latency, throughput and area overhead. The experimental results show that, the proposed router with on-the-fly VC allocation can reduce the network latency by 40.9%, and improve throughput by 47.6% as compared to the conventional VC router. In comparison with the look-ahead speculative router, it improves the throughput by 8.8% with 16.7% reduction of area for control logic.

This paper proposes a high-speed input and output buffering ATM switch, named the tandem-crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at all crosspoints. The TDXP switch architecture offers several advantages. First, the TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. These merits make it easy to implement a high-speed ATM switch. Numerical results show that the TDXP switch can effectively eliminate HOL blocking and achieve high throughput. In addition, we discuss how TDXP switches can be combined to form larger switches in a cost-effective way. We clarify the relative advantages of the crossbar switch configuration and the three-stage Clos switch configuration in achieving a specific throughput. Because the three-stage Clos switch configuration is not strictly non-blocking, we introduce a nearly non-blocking condition and evaluate switch throughput under the condition. The evaluation shows that crossbar switch configuration becomes more cost effective as the throughput of individual switch LSIs, which depends on device technologies, increases.

Network-on-Chip (NoC) design tries to keep a balance between network performance and physical implementation flexibility. The adoption of Virtual Channels (VC) holds promise for scalable NoC design. VCs allow for traffic separation and isolation, enable deadlock avoidance and improve network performance. In this paper, we present ElastiNoC, a novel distributed VC-based router architecture that enjoys all the benefits offered by VCs and leads to efficient silicon-aware implementations. The proposed architecture utilizes an efficient buffering strategy and allows for modular pipelined organizations that increase the clock frequency. Moreover, it offers maximum freedom in terms of physical placement, by allowing the NoC components to be physically spread throughout the chip, irrespective of the network topology. The combined effect of all supported features enables significant delay reductions under equal performance, when compared to state-of-the-art VC-based NoC implementations. Moreover, the careful addition of self-test structures allows ElastiNoC to enjoy fully distributed Built-In Self Testability (BIST), where testing unfolds in phases and reaches high fault coverage with small test application time.

Networks-on-chip (NoCs) were developed to meet the communication requirements of large-scale systems. The majority of current NoCs spend considerable area and power for router buffers. In our past work, we have developed elastic buffer (EB) flow control which adds simple control logic in the channels to use pipeline flip-flops (FFs) as EBs with two storage locations. This way, channels act as distributed FIFOs and input buffers are no longer required. Removing buffers and virtual channels (VCs) significantly simplifies router design. Compared to VC networks with highly-efficient custom SRAM buffers, EB networks provide an up to 45 percent shorter cycle time, 16 percent more throughput per unit power, or 22 percent more throughput per unit area. EB networks provide traffic classes using duplicate physical subnetworks. However, this approach negates the cost gains or becomes infeasible for a large number of traffic classes. Therefore, in this paper we propose a hybrid EB-VC router which provides an arbitrary number of traffic classes by using an input buffer to drain flits facing severe contention or deadlock. Thus, hybrid routers operate as EB routers in the common case, and as VC routers when necessary. For this reason, the hybrid EB-VC scheme offers 21 percent more throughput per unit power than VC networks and 12 percent than EB networks.

MPTCP is a very promising protocol for improving throughput and reliability for a multi-interface device. However, the throughput of MPTCP is unexpectedly degraded when the characteristics of subflows, such as bandwidth or delay, are different because of HoL blocking at the MPTCP receiver buffer. Therefore, in order to solve this problem, in this paper, we monitor the receiver's reordering buffer to detect the HoL blocking phenomenon and to retransmit the problematic HoL (Head of Line) packet using the fast path. During bufferbloat, the data transmission of the long-RTT path is suppressed and the path re-activation timing is monitored by transmitting the probe packet pairs. Simulation results show that the proposed algorithm not only improves performance degradation due to long-RTT path in bufferbloat situation but also reduces data transmission time.

Network on Chip (NoC) is an emerging design platform for on chip connections which overcomes issues faced by conventional bus build communication. The main aim in design of any NoC is to reduce average latency and deflection rate without reducing the operating speed. To overcome the surge in design area as well as Static and Dynamic power consumption issues in case on normal VC (Virtual Channel) based router, deflection routing concept has been suggested. The routing process used in case of BLESS (Buffer Less Router) depends upon deflection of packets to an unintended port. To curtail excess power consumption and design area, researchers have come up with buffer less and littlest buffer router. In this paper Tiled Chip Multiple Processor (TCMP) and CHIPPER router parameter details are discussed. Permutation deflection logic is used in this paper. Results shows that as compared to normal VC Buffer router, CHIPPER Router reduces Normalized Router area by 36.2% compared to BLESS Router, Normalized Critical Path is reduced by 29.1% while is almost same as compared to a normal VC Buffer Router

Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting contention and congestion information to load balance the traffic. However, most prior works do not consider balancing the traffic load during switch allocation. Due to the lack of congestion information in switch allocation stage, switch allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of switch. In this paper, we propose CCAS, a new switch allocation strategy to add the contention and congestion information into the switching process to load balance the traffic and achieve efficient switch allocation. We carefully design CCAS to balance the trade-off between traffic load balance and the matching efficiency in switch allocation. We evaluate our design under synthetic traffic and traces of PARSEC benchmarks. Our evaluations show that CCAS can achieve remarkable latency reduction compared to other switch allocation strategies.

Fault tolerant routing algorithms, are a key concern in on-chip communication. This paper examines fault tolerant communication algorithms for use in network-on-chip (NoC). We propose an improved wormhole-switched routing algorithm in 2-dimensional mesh based on f-cube3 algorithm to decrease message latency. The existing key concept is using numbers of virtual channels (VC) via a physical link. This paper proposes some improvements to make use of VCs while the numbers of them are fixed. We show that when a message is not blocked by fault, all VCs could be used; f-cube3, however, uses only one of the VCs. Furthermore, the strength of the improved algorithm is demonstrated by comparing results of simulations in both f-cube3 and the improved algorithm if-cube3.

With the advancement in CMOS technology and multiple processors on the chip, communication across these cores is managed by a Network on Chip (NoC). Power and performance of these NoC interconnect have become a significant factor. In particular, the buffers used at every port consume considerable dynamic as well as leakage power. This paper attempts to reduce leakage power consumption of NoC buffers by use of non-volatile memory (NVM) technology based STT-RAM buffers. STT-RAM technology has the advantage of high density and low leakage but suffers from high write energy and low endurance. In particular, if some buffers get written more number of times compared to some other buffers, the heavily written buffers may wear out faster compared to others. This has an impact on the lifetime of the router as a whole. Here we propose a virtual channel (VC) allocation policy that helps to uniformly distribute the writes across the buffers to improve their effective lifetime. Pure STT-RAM buffers, however, impact the network latency. In order to mitigate this, we propose a hybrid policy that uses an alternative VC made of SRAM technology in case of heavy network traffic. Experimental evaluation on full system simulation shows that the proposed policy reduces the write variation by 99% and improves lifetime by 3.4 times and 24 times, respectively for both the proposals. We also get respectively 93% and 90% gains in the EDP.