Scalable driver I/O macromodels for statistical analysis

A nonlinear system of hybrid fractional differential equations with application to fixed time sliding mode control for Leukemia therapy

New driver and receiver circuits for WSI systems have been realized with the advantages of short delay, small area and low power dissipation. These concepts are compared to conventional driver circuits.

This paper presents a comprehensive evaluation of fabrication techniques for the integration of coils into textiles, for the purpose of enabling low-power wireless power transfer; for example, the powering of on-body monitoring devices, such as heart-rate monitors. Key electrical parameters of the coils required to maximize power transfer efficiency are identified from theory. Flexible coils have been fabricated using standard processes widely used in the textile industry, such as screen printing and embroidery. The screen printed coils were fabricated with a silver-polymer ink on a printed interface layer; the embroidered coils were fabricated using a variety of conductive threads formed by coating textile fibers and through the use of copper fibers. These coils have been experimentally characterized and evaluated for use in wireless power transfer applications. The effects of coil geometry and separation on the dc–dc power transfer efficiency using Qi standard compliant driver and receiver circuits are reported.

This paper compares the major classes of chip-to-chip and on-chips interconnections used in high-performance computers and communication systems and reviews their electrical characteristics. Measurement results of dielectric loss are shown and the attenuation is compared for printed-circuit-board, glass-ceramic, thin-film, and on-chip wiring. Simulation results are shown with representative driver and receiver circuits, guidelines are given for when losses are significant, and predictions are made for the sustainable bandwidths on useful wiring lengths.

This paper presents the characterization of an input/output interface circuit designed for multi-purpose pattern recognition applications compatible with low-voltage fully differential signaling (LVDS) standard. The driver and receiver circuits described in this work has been designed and fabricated in a 28 nm CMOS technology. The prototype chip has been mounted on a printed circuit board with physical characteristics similar to the real application case and fully validated up to 1 Gb/s with input random patterns.

Novel low‐power circuits based on low swing voltage technique, in the internal nodes of bus architectures, are proposed. Different classes of driver/receiver and repeater circuits are presented. They are implemented on conventional CMOS technology. The proposed technique is based on inserting a variable number of MOSFET transistors in the driver circuits, causing variable low swing voltage levels in the output of the driver circuits. In order to re‐pull up the low swing voltage to full swing, innovated high‐speed, crosscoupled latch voltage receiver circuits are proposed. In applications having high load capacitance due to long interconnections, novel repeater circuits, based also on low swing voltage technique, are introduced. The difference between the values of threshold voltage of the nMOS transistor and the pMOS transistors is exploited to decrease the power dissipation. The effect of the proposed technique in noise margins is also analysed.

The continuing increase in circuit density and speed is placing an even greater burden on the electrical performance of intra-system interconnections. Both multiprocessor computer systems and communication networks are expected to require the propagation of 100 Mb/s-1 Gb/s type of data rates over lengths greater than 50 cm on relatively inexpensive card-on-board technologies. It is important to understand the key limiting factors and the directions needed for future development. In this paper we investigate the electrical performance of available high-density printed-circuit cards or boards and highlight the effect of skin-effect and dielectric losses. Several types of commercially available high-performance shielded pinned connectors for large size panels are modelled and their contributions to signal distortion and crosstalk are shown. The complete interconnection path starting from the driver circuit on one card and traversing representative board path to the receiver circuit on another card is analyzed and the practical extendibility limitations are discussed. Experimental results on specially built card and connector paths that emulate the actual use are compared with modelled waveforms.

We present the use of visible light as an alternative to wireless radio communication. We use common data encryption techniques followed by modulation of the signal using Orthogonal Frequency Division Multiplexing. The modulated signal is used to drive common Light Emitting Diodes which transmit a binary bit-stream in the form of light, through air as the medium. A photo detector, used at the receiver, along with a driver circuit and the appropriate decryption block is used to get back the original data. LED bulbs are used as transmitters and the intensity of the LEDs is varied at very high rate, using OFDM modulation technique to encode the image data, such that the intensity appears constant to the human eye. Thus, apart from providing illumination, the LED bulb transmits data at high rates. The sensitive receiver circuit is designed to detect these small instantaneous changes in the LED intensity and hence decode the received data, thereby reproducing the data in its original quality. The integration of high response Silicon PIN Photodiodes with signal processing tools makes this possible. Specific design measures prevent ambient light from interfering with the demodulation process at the receiver. Although this method can be currently used for short range, future developments can really expand its scope.

Electromagnetic interference (EMI) signals, which radiate in the environment and cause the malfunction of electronic devices in proximity, are generated due to the common mode (CM) noise in differential circuits. This CM noise is produced because of the imbalance in the charging and discharging paths of the driver and equalizer circuits in the transmitter. However, the effects of the equalizer on CM noise have not been examined. This paper systematically investigates the effect of different feed forward equalizer (FFE) configurations on EMI-related CM noise in a 56-Gbps four-level pulse-amplitude modulation (PAM-4) optical transmitter, aiming to provide an optimized configuration with low CM noise and power consumption, while providing high compensation. The simulation results show that an asymmetric equalizer significantly improves the compensation performance. However, the offset in differential pair of output stage should be minimized to decrease the CM noise generated from the FFE.

The electrical performance of an integrated circuit is impacted by (a) environmental factors which include variations in power supply voltage and temperature, and(b) physical factors caused by processing and mask imperfections. Only the physical sources of variability, denoted P, are dealt with. P includes device and wire model parameters such as V/sub th/, T/sub ox/ and R/sub s/.

Scaling of the on-chip feature size and power supply voltage have significantly reduced the noise margins of an integrated circuit and have aggravated the effects of process and enviromental variations. These effects can introduce delay variations on the signals within a circuit, possibly causing a violation of the timing constraints in a clocked register that can lead to system malfunctioning. The effects of parameter variations on the timing characteristics of adder structures are investigated in this paper. The sensitivity of the critical delay of sum and carry signals under variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different adder architectures.

ABSTRACTThis paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (< 200fs) are introduced and compared in a 0.18µm commercial CMOS process.

This paper introduces the inverse synthetic aperture radar(ISAR) imaging technique for rear view target of an automobile, which uses both linear frequency modulation-frequency shift keying(LFM-FSK) waveform and monopulse tracking. LFM-FSK waveform consists of two sequential stepped frequency waveforms with some frequency offset, and thus, can be used to generate ISAR images of rear view target of an automobile . However, ISAR images can often be blurred due to non-uniform change rate of relative aspect angle between radar and target. In order to address this problem, one-dimensional(1-D) Lagrange inter-polation technique in conjunction with angle information obtained from the monopulse tracking is applied to generate uniform data across the radar’s aspect angle. Simulation results show that the proposed method can provide focused ISAR images. Key words: ISAR, LFM-FSK Waveform, Automotive Radar o;p qrs htuvQY>wxWy_(‘ITz{|}~* x’(;p<h:c€(NIPA-2013-H0203-13-1001).‚ ƒ„ h@tGH th(Department of Electrical Engineering, Pohang University of Science and Technology) Manuscript received November 7, 2013 ; Revised December 3, 2013 ; Accepted December 4, 2013. (ID No. 20131107-111)Corresponding Author: Kyung-Tae Kim (e-mail: kkt@postech.ac.kr)

A lattice Boltzmann method on nonuniform mesh is developed for the simulation of incompressible flows. The computation mesh is uncoupled from the lattice. The particle distribution function on the mesh is obtained using the Lagrange interpolation technique at each time step. Comparison with the finite difference solutions for the two-dimensional driven cavity flow and the experimental results for flow around a circular cylinder shows that the present scheme not only can predict the flow separation characteristic satisfactorily with much less mesh but also increase the computational stability. The influence of the mesh structure and interpolation on the results will also be discussed.