Scalable hardware designs for Median Filters based on separable sorting networks

Coupled resonator circuits are the basis for the design of many bandpass microwave filters. Design techniques used for two-port coupled resonator circuits are extended here to multiple output circuits such as power dividers and diplexers. The design approach is based on synthesis of coupling matrix for multiple coupled resonators with multiple outputs using gradient-based optimisation. It allows the synthesis of power dividers with arbitrary power division, as well as diplexers and multiplexers with novel topologies. Since there is no need to use separate energy distribution networks such as circulators, manifolds or other junctions, the components can be miniaturised. An X-band unequal power divider and diplexer have been designed and realised using waveguide cavity resonators to confirm the new design methodology.

Scalable hardware implementing high-radix Montgomery multiplication algorithm

Problem statement: Image sensors and communication channels often introduce impulse noise in image transmission. The most common filters available to remove such noise are median filter and its variants but the major drawbacks identified with them are blurring of edge detail and low noise suppression. To preserve the sharp and useful information in the image, the filtering algorithms are required to have intelligence incorporated in them. Approach: This research proposed a particle swarm optimization based approach in the design of filter. The filter weights were adapted and optimized directionally to restore a corrupted pixel in a mean square sense. Results: This results in replacement of noisy pixels by near originals along its edge direction. Various objective parameters like Mean Absolute Error (MAE), percentage of noise elimination, percentage of pixels spoiled showed that the proposed recursive no-reference filter performs 4dB better than the competing filters. Conclusion: This research aimed at presenting a new filtering framework for impulse noise removal using Particle Swarm Optimization (PSO).

The paper concentrates on the horizontal directional drilling attitude measuring system which consists of acceleration sensors and magnetoresistive sensors. It does detailed analyses about attitude angle measurement error caused by the sensor manufacturing and installation error, and make compensation from two aspects of hardware and software according to the error sources. In these situations, for example: weak signals in the geomagnetic field measurements and vulnerable to the interference of changes of the current source in the environment, the authors will add arithmetic average filtering program on the basis of the software, besides in the hardware design with filters and in the software design of arithmetic average filtering and median value filter and amplitude limit filtering MATLAB simulation and actual testing; the authors do further analysis about magnetic deviation caused by the influence of magnetic material, and correct the magnetic deviation by the method of ellipse fitting. It has been certificated in the experiments that these measures improve the measurement precision of the system.

This paper presents a method for the design of median-type filters that achieve the maximum noise attenuation under structural constraints imposed by the requirement of preserving certain signal or image features. As compared to the design of optimal weighted median (WM) filters, this method is extremely simple get general enough and an analytic, closed-form representation of its Boolean function can be obtained. Furthermore, it is demonstrated that, under the same set of structural constraints, the filters designed in this way perform much better in removing noise of any kind than the optimal WM filters. Also, the improvement in the impulsive noise environment is very significant, as is demonstrated by an image enhancement application. >

Image filtering, which removes or reduces noises from the contaminated images, is an important task in image processing. In the recent years, evolutionary design of image filters that provides adaptive and hardware implement able solutions has been received a lot of attentions. This study deals with the design of multiple evolvable hardware (EHW) based image filters using fuzzy relations. Two indicators, similarity and divergence, are defined as fuzzy sets for describing the relations of pixels contained in a sliding window. In the proposed method, each pixel to be recovered is analyzed by the fuzzy relations and labeled as the associated noise type. Multiple EHW-based image filters, each of which is trained supervisedly by the pixels belonging to the same noise type, are built simultaneously. Because each image filter is dedicated to a specific type of noise, it can recover pixels of the noise type more accurately. With the proposed method, the efficiency of training EHW models and accuracy of image filtering are both improved. This paper evaluates and compares the performance of the proposed method with other ones. To our best knowledge, this is the first attempt to use fuzzy relations for noise categorization for the design of EHW-based image filters.

Image processing has an important role in signal processing. The occurrence of noise in the image can degrade its quality and can cause loss of information. In this paper, design of Gaussian, mean, and median filters is considered. Gaussian and mean filters are linear filters and are designed using convolution between 3 × 3 image pixel matrix and kernel matrix. The median filter is a nonlinear filter. An SRAM-based FPGA implementation of such a filter is susceptible to memory bit flips that are caused by single-event upsets (SEUs). Hence, a protection method is needed to ensure proper working of the median filter. Here, the median filter design proposed in (Aranda et al. in J. IEEE Transactions on Nuclear Science 64:2219–2226, 2017 [7]) is used to check if the median value obtained is within a dynamic range. The performance of these three filters is evaluated by considering image quality metrics such as PSNR and correlation coefficient with four different noises. The results show choice of the filter for denoising, based on the type of noise present in the image. In recent times, FPGA technology has become a reliable method for implementing image processing algorithms due to their fast response compared to image processing in MATLAB. The noisy image to pixel conversion is done in MATLAB. The 3 × 3 sliding window approach is used for filter coding in Verilog, and the FPGA synthesis on virtex5 is done with Xilinx ISE 14.5. The images are reconstructed with filtered pixels in MATLAB.

Median filters commonly used in image processing applications for the removal of impulse noise. Over the years so many median filters such as are separable median filters, recursive median filters, weighted median filters, max-median filters and multistage median filters were developed. Sorting networks are of major concern for real time hardware implementation of filters. Sorting is a computationally expensive operation as it consumes large area, speed and power. In this work, effective VLSI hardware implementation has been proposed as an economical solution for sorting networks in terms of area speed, power. The proposed work uses a new carry select comparator in the first section which uses compare and swap functions and its pipelined version in second section, thereby reducing the complexity of the sorting networks. The proposed Carry select comparator uses one half subractor, 7 full subractor, few multiplexers and inverters. The proposed algorithm will definitely overcome the problems by performing median calculation within 7 clock cycles. This work had been compared with existing carry select logic and its pipelined version occupies which occupies less area, consumes low power and works at 113.225 MHz for the device Devices XC2s100e-7tq144.

Median filters are a widely-used tool in graphics, imaging, machine learning, visual effects, and even audio processing. Currently, very-small-support median filters are performed using sorting networks, and large-support median filters are handled by O (1) histogram-based methods. However, the constant factor on these O (1) algorithms is large, and they scale poorly to data types above 8-bit integers. On the other hand, good sorting networks have not been described above the 7 X 7 case, leaving us with no fast way to compute integer median filters of modest size, and no fast way to compute floating point median filters for any size above 7 X 7. This paper describes new sorting networks that efficiently compute median filters of arbitrary size. The key idea is that these networks can be factored to exploit the separability of the sorting problem - they share common work across scanlines, and within small tiles of output. We also describe new ways to run sorting networks efficiently, using a sorting-specific instruction set, compiler, and interpreter. The speed-up over prior work is more than an order of magnitude for a wide range of data types and filter sizes. For 8-bit integers, we describe the fastest median filters for all sizes up to 25 X 25 on CPU, and up to 33 X 33 on GPU. For higher-precision types, we describe the fastest median filters at all sizes tested on both CPU and GPU.

0.5-V DTMOS median filter

-- Digital watermarking plays a critical role in ensuring the protection, authenticity, and integrity of multimedia content, particularly in today's data-driven environment. In this paper, we present a solution for the watermarking of grayscale images utilizing the Discrete Wavelet Transform (DWT) technique. Our approach focuses on embedding watermark information into the frequency components of the image to achieve a balance between imperceptibility and robustness against common signal processing attacks. A complete software-based implementation of the watermark embedding and extraction process has been developed and evaluated using standard grayscale images. Additionally, we propose a high-level VLSI architecture for real-time implementation of the DWT-based watermarking system, emphasizing efficient resource utilization, parallelism, and low power design. Extensive simulations demonstrate the effectiveness of the DWT-based watermarking method, achieving strong imperceptibility and resilience. This research contributes to the growing field of digital image security by presenting a practical approach to scalable hardware design and opens new directions for future real-time, hardware-accelerated watermarking applications. Key Words: Digital watermarking, Discrete Wavelet Transform (DWT), Grayscale images, VLSI architecture, Image security, Frequency domain, Robustness, Imperceptibility, Hardware design, Real-time systems.

The subject of this thesis is scalability and persistence. A convergence of computing and communications technologies has lead to the ‘information explosion’. Demand for information has grown at an unprecedented pace, placing pressure on the scalability of information servers. At the same time there has been a revolution in switching technology which has seen the once exotic tightly coupled distributed memory computer become widely available through commodity components. These two developments in computing and communications technologies come together, the former bringing with it the challenge of constructing systems capable of scaling to address the spiraling demand for information, and the latter offering a scalable hardware architecture upon which such systems can be based. The most elegant approach to persistent data management lies in the use of orthogonal persistence. Orthogonally persistent programming languages bring together the disparate concerns of programming languages and databases by making the persistence of data a property orthogonal to all others. However, while users are presented with a unified view of the concerns, implementers of orthogonally persistent programming languages must confront the disparity head-on. The quest to design efficient, scalable, orthogonally persistent systems represents a bringing together of the challenge of constructing systems capable of scaling, with the challenge of constructing orthogonally persistent systems. This raises the deeper question as to whether there exists a generalized framework for scalable persistent system design. The framework will bring together the fundamental concerns of concurrency, replication, coherency, latency, and stability. The major result in this thesis is the description of such a framework. The fundamental concerns are met through a reference architecture based on caching, atomicity, and a layered software architecture. The framework has been realized in the form of the Persistent Store Interface (PSI). The effectiveness of PSI for scalable persistent system construction is demonstrated through a number of experiments with PSI prototypes, both stand-alone and distributed. In addition, two supporting experiments are described, one examining the issues of designing scalable stores that present users with a single store image and the other examining mechanisms for scalable coherency and recovery. The development of a generalized and practical framework for scalable persistent system design in this thesis gives cause for optimism that orthogonal persistence will play an important role in the future of scalable information management.

The paper deals with evolutionary design of impulse burst noise filters. As proposed filters utilize the filtering window of 5times5 pixels, the design method has to be able to manage 25 eight-bit inputs. The large number of inputs results in an evolutionary algorithm not able to produce reasonably working filters because of the so-called scalability problem of evolutionary circuit design. However, the filters are designed using an extended version of Cartesian Genetic Programming which enables to reduce the number of inputs by selecting the most important of them. Experimental evaluation of the method has shown that evolved filters exhibit better results than conventional solutions based on various median filters.

This paper presents a new design of 2D median filter. The filter implements a simple conditional filtering technique that executes fewer computations than related formulations while achieving superior image quality. Experimental FPGA implementations of the proposed filtering scheme for window sizes of (3×3) and (5×5) are very compact, fast and consume low-power.

SAccO: An implementation platform for scalable FPGA accelerators