Scheduling Constrained-Deadline Sporadic Parallel Tasks Considering Memory Contention

The generalized multiframe task model (GMF) extends the sporadic task model and multiframe task model. Each frame in the GMF model contains an execution time, a relative deadline, and a minimum inter-arrival time. These parameters are fixed after task specification time in the GMF model. However, multimedia and adaptive control systems may be overloaded and no longer stabilized when the task parameters in such systems are not flexible. In order to address this problem, deadlines and periods of frames may change to alleviate temporal overload, e.g., in the parameter adaptation and elastic scheduling model. In this paper, we propose a new model GMF-PA (the GMF model with parameter adaptation). This model allows task parameters to be flexible in arbitrary-deadline systems. A necessary schedulability test based on mixed-integer linear programming is given to check the schedulability under EDF scheduling and optimally assign frame deadlines and periods at the same time. We also prove that the test is a sufficient and necessary schedulability test when frame deadlines and periods must be integers. An approximation algorithm is also deployed to reduce computational running time and indicates a sufficient schedulability test in general. The speed-up factor of our approximation algorithm is $$1+\epsilon $$ where $$\epsilon $$ can be arbitrarily small, with respect to the exact schedulability test of GMF-PA tasks under EDF. We also apply the GMF model to self-suspending tasks. By extending recent work on scheduling self-suspending tasks, we remove the assumption that frame deadlines are equally assigned in self-suspending tasks, and the system is extended from constrained-deadline systems to arbitrary-deadline systems. We have done extensive experiments to show that the schedulability ratio is improved using our techniques in our GMF-PA model.

The generalized multiframe task model (GMF) extends the sporadic task model and multiframe task model. Each frame in the GMF model contains an execution time, a relative deadline, and a minimum inter-arrival time. These parameters are fixed after task specification time in the GMF model. However, multimedia and adaptive control systems may be overloaded and no longer stabilized when the task parameters in such systems are not flexible. In order to address this problem, deadlines and periods may change to alleviate temporal overload, for example in the parameter adaption and elastic scheduling model. In this paper, we propose a new model GMF-PA (the GMF model with parameter adaption). This model allows task parameters to be flexible in arbitrary-deadline systems. A necessary schedulability test based on mixed-integer linear programming (MILP) is given to check the schedulability under EDF scheduling and optimally assign deadlines and periods at the same time. We also prove that the test is a sufficient and necessary schedulability test when task parameters must be integers. An approximation algorithm is also deployed to reduce computational running time. The speed-up factor of our approximation algorithm is 1+a#x0395; where a#x0395; can be arbitrarily small, with respect to the exact schedulability test of GMF-PA tasks under EDF. We also apply the GMF model to self-suspending tasks. By extending recent work on scheduling self-suspending tasks, we remove the assumption that deadlines are equally assigned in self-suspending tasks, and the system is extended from constrained-deadline systems to arbitrary-deadline systems. We have done exhaustive experiments to show that the schedulability ratio is improved using our techniques in our GMF-PA model.

Directed forgetting is a laboratory task in which subjects are explicitly cued to forget certain items and remember others. Volitional control over the contents of memory has been used to study clinical disorders, with successful intentional control of memory being a hallmark of a healthy mind. Yet the degree of volitional forgetting over the content of visual long-term memory is unclear when compared to words. Different kinds of visual stimuli (e.g., abstract symbols, line drawings, scenes) may not equally be susceptible to voluntary control in memory, and intentional forgetting studies have shown both twice as much forgetting of pictures compared to words (think/no-think task) and half as much forgetting of pictures compared to words (directed forgetting task). In the present study, we systematically test volitional control over pictures of everyday objects using item-method directed forgetting procedures. We find that subjects are able to intentionally prioritize memory for pictures cued as to be remembered over pictures cued to be forgotten. Here we show that directed forgetting effects are observed using pictures of everyday objects (albeit to a weaker extent compared to directed forgetting of words), suggesting increased confidence for generalization of directed forgetting literature to real-world applications. However, we caution clinical applications of intentional memory control until the underlying direction causing this effect (upregulation of remember-cued items or downregulation of forget-cued items) is known.

Emerging non-volatile memories (NVM), such as phase change memory (PCM) and Resistive RAM (ReRAM), incorporate the features of fast byte-addressability and data persistence, which are beneficial for data services such as file systems and databases. To support data persistence, a persistent memory system requires ordering for write requests. The data path of a persistent request consists of three segments: through the cache hierarchy to the memory controller, through the bus from the memory controller to memory devices, and through the network from a remote node to a local node. Previous work contributes significantly to improve the persistence parallelism in the first segment of the data path. However, we observe that the memory bus and the Remote Direct Memory Access (RDMA) network remain severely under-utilized because the persistence parallelism in these two segments is not fully leveraged during ordering. In this paper, we propose a novel architecture to further improve the persistence parallelism in the memory bus and the RDMA network. First, we utilize inter-thread persistence parallelism for barrier epoch management with better bank-level parallelism (BLP). Second, we enable intra-thread persistence parallelism for remote requests through RDMA network with buffered strict persistence. With these features, the architecture efficiently supports persistence through all three segments of the write datapath. Experimental results show that for local applications, the proposed mechanism can achieve 1.3X performance improvement, compared to the original buffered persistence work. In addition, it can achieve 1.93X performance improvement for remote applications serviced through the RDMA network.

Chapter 13 - DRAM Memory Controller

Image processing applications tend to access their data non-sequentially and reuse that data infrequently. As a result, they tend to perform poorly on conventional memory systems due to high cache and TLB miss rates and are particularly sensitive to the growing latency of main memory. In this paper, we analyze the memory performance of three image processing algorithms (volume rendering, image warping, and image filtering) on both a conventional memory system and on the Impulse memory system. The Impulse memory system allows application software to control how, when, and where data are loaded into a conventional processor cache. It does this by letting software configure how the memory controller interprets the physical addresses exported by the processor, which enables an application to dynamically change how data are fetched. Sparse data can be accessed densely, which improves both cache and TLB utilization, and memory latency is hidden by prefetching data within the memory controller. We find that for these image processing codes, using an Impulse memory system yields speedups of 40% to 226% over an otherwise identical machine with a conventional memory system.

Contention for shared resources in High-Performance Computing (HPC) clusters occurs when jobs are concurrently executing on the same multicore node (there is a contention for shared caches, memory buses, memory controllers and memory domains). The shared resource contention incurs severe degradation to workload performance and stability and hence must be addressed. The state-of-the-art HPC clusters, however, are not contention-aware. The goal of this work is the design, implementation and evaluation of a virtualized HPC cluster framework that is contention aware.

Memory system performance is an important factor in determining overall system performance. The design of key components of the memory system, such as the memory controller, becomes more important as memory performance becomes a limiting factor in high performance computing. This work focuses on the design of a unit which sends control signals to Double Data Rate Synchronous Dram (DDR SDRAM). The design is based on established concepts such as access reordering. A novel, adaptive page policy based on a machine learning algorithm has been developed in this work and evaluated with traditional page policies. the work illustrates some of the design trade-offs in a memory controller and the performance of the designs when using real application address traces.The results show that access reordering improves the performance of DDR SDRAM compared to in-order scheduling (up to 50% improvement) and that scheduling multiple requests can result in latency hiding. The dynamic page policy approximates the best static page policy in most cases.

Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided memory-bound applications of commercial importance, such as database and multimedia programs.

Cores in a chip-multiprocessor (CMP) system share multiple hardware resources in the memory subsystem. If resource sharing is unfair, some applications can be delayed significantly while others are unfairly prioritized. Previous research proposed separate fairness mechanisms in each individual resource. Such resource-based fairness mechanisms implemented independently in each resource can make contradictory decisions, leading to low fairness and loss of performance. Therefore, a coordinated mechanism that provides fairness in the entire shared memory system is desirable. This paper proposes a new approach that provides fairness in the entire shared memory system , thereby eliminating the need for and complexity of developing fairness mechanisms for each individual resource. Our technique, Fairness via Source Throttling (FST), estimates the unfairness in the entire shared memory system. If the estimated unfairness is above a threshold set by system software, FST throttles down cores causing unfairness by limiting the number of requests they can inject into the system and the frequency at which they do. As such, our source-based fairness control ensures fairness decisions are made in tandem in the entire memory system. FST also enforces thread priorities/weights, and enables system software to enforce different fairness objectives and fairness-performance tradeoffs in the memory system. Our evaluations show that FST provides the best system fairness and performance compared to four systems with no fairness control and with state-of-the-art fairness mechanisms implemented in both shared caches and memory controllers.

In the design of time-critical applications, schedulability analysis can be used to define the feasibility region of tasks so that optimization techniques can find the best design solution that satisfies the deadlines. This method has been applied to obtain the optimal task implementation, priority assignment or placement of tasks onto CPUs in previous work. The definition of the feasibility region based on response time calculation requires many integer variables and is too complex for solvers. Approximation techniques have been used to define a convex subset of the feasibility region, often used in conjunction with branch and bound to compute sub-optimal solutions. In this paper, we provide an improved and simpler feasibility analysis method that allows an exact definition of the feasibility region in Mixed Integer Linear Programming (MILP) optimization methods. The encoding of the feasibility region using our method requires a significantly smaller number of binary variables and is viable for the treatment of industrial-size problems as shown by the experiments.

In multi-core systems, main memory is a major shared resource among processor cores. A task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared main memory system. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to reduce this interference and provide an upper bound on the worst-case interference on a multi-core platform that uses a commercial-off-the-shelf (COTS) DRAM system. We explicitly model the major resources in the DRAM system, including banks, buses, and the memory controller. By considering their timing characteristics, we analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel. We find that memory interference can be significantly reduced by (i) partitioning DRAM banks, and (ii) co-locating memory-intensive tasks on the same processing core. Based on these observations, we develop a memory interference-aware task allocation algorithm for reducing memory interference. We evaluate our approach on a COTS-based multi-core platform running Linux/RK. Experimental results show that the predictions made by our approach are close to the measured worst-case interference under workloads with both high and low memory contention. In addition, our memory interference-aware task allocation algorithm provides a significant improvement in task schedulability over previous work, with as much as 96 % more tasksets being schedulable.

In the modern chip-multiprocessor system, main memory is a shared resource among multiple concurrently executing threads/applications. The memory scheduling algorithms are developed to resolve memory contention by arbitrating memory access in such a way that competing threads progress at a relatively fast and even pace, resulting in high system throughput and fairness. This paper presents a new memory scheduling algorithm called Time-Based Least Memory Intensive scheduling (TB-LMI) that addresses system throughput and fairness with the goal of achieving a better throughput and limiting the unfairness. The main idea is to prioritize threads according to their memory contentions every pre-defined period of cycles to improve system throughput and to guarantee fairness. We evaluate TB-LMI on a variety of multi-programmed workloads with different queue sizes of memory controllers and compare its performance to four previously proposed scheduling algorithms. TB-LMI achieves the best system throughput and fairness. On 8-core system, TB-LMI improves system throughput and fairness on average by 4.22% and 11.7% respectively compared to Thread Cluster Memory scheduling (TCM) (previous work providing the best system throughput and fairness). Our newly proposed technique adds negligible area and logic overhead to the Memory Controller compared to the benefits on the system performance.

A large number of criteria have been proposed for determining when a behavior has become automatic. Almost all of these were developed before the widespread acceptance of multiple memory systems. Consequently, popular frameworks for studying automaticity often neglect qualitative differences in how different memory systems guide initial learning. Unfortunately, evidence suggests that automaticity criteria derived from these frameworks consistently misclassify certain sets of initial behaviors as automatic. Specifically, criteria derived from cognitive science mislabel much behavior still under the control of procedural memory as automatic, and criteria derived from animal learning mislabel some behaviors under the control of declarative memory as automatic. Even so, neither set of criteria make the opposite error-that is, both sets correctly identify any automatic behavior as automatic. In fact, evidence suggests that although there are multiple memory systems and therefore multiple routes to automaticity, there might nevertheless be only one common representation for automatic behaviors. A number of possible cognitive and cognitive neuroscience models of this single automaticity system are reviewed. WIREs Cogn Sci 2012, 3:363-376. doi: 10.1002/wcs.1172 For further resources related to this article, please visit the WIREs website.

For real-time systems, most of the analysis involves efficient or exact schedulability checking. While this is important, analysis is often based on the assumption that the task parameters such as execution requirements and inter-arrival times between jobs are known exactly. In most cases, however, only a worst-case estimate of these quantities is available at the time of analysis. It is therefore imperative that schedulability analysis hold for better parameter values ( Sustainable Analysis ). On the other hand, if the task or system parameters turn out to be worse off, then the analysis should tolerate some deterioration ( Robust Analysis ). Robust analysis is especially important, because the implication of task schedulability is often weakened in the presence of optimizations that are performed on its code, or dynamic system parameters. In this work, we define and address sustainability and robustness questions for analysis of embedded real-time software that is modeled by conditional real-time tasks. Specifically, we show that, while the analysis is sustainable for changes in the task such as lower job execution times and increased relative deadlines, it is not the case for code changes such as job splitting and reordering. We discuss the impact of these results in the context of common compiler optimizations, and then develop robust schedulability techniques for operations where the original analysis is not sustainable.