Scheduling real-time tasks for dependability

We consider using hardware and software redundancy to guarantee task deadlines in a hard real-time mu1 tiprocessor system even in the presence of processor failures. A set of scheduling requirements for the real-time fault-tolerant multiprocessor scheduling problem is first identified and a heuristic algorithm is then proposed to solve the problem. Experimental results show that the algorithm finds optimal solutions in most of the cases.

In a real-time system with both hard deadline periodic tasks and soft deadline aperiodic tasks, hard deadline tasks must be guaranteed to meet their deadlines and soft deadline tasks are serviced in a best-effort manner. To schedule soft deadline aperiodic tasks in dynamic priority systems, one can assign a virtual deadline like the TBS algorithm or use capacity servers like the DPE algorithm. Both approaches have their own advantages, and we cannot say which one is better in terms of response time. In some cases, TBS provides shorter response time than DPE server. In other cases, the reverse may happen. In this paper, we propose a combined approach to improve the response time of soft deadline aperiodic tasks. The proposed method combines the deadline assignment and the capacity server approach. When there is enough capacity available for aperiodic tasks, the aperiodic tasks are served by capacity servers. Otherwise, our method assigns a deadline and schedule aperiodic task together with periodic tasks by EDF algorithm. In the worst case, the proposed method provides response time no later than TBS. Experimental results show that the proposed approach improves the responsiveness of soft deadline aperiodic tasks.

DES based Modeling and Fault Diagnosis in Safety-critical Semi-Partitioned Real-time Systems

We introduce a new set of dynamic scheduling algorithms for scheduling and guaranteeing the deadline compliance of a set of aperiodic real-time tasks on a uniprocessor architecture. The task model selected is that of non-preemptable tasks with arbitrary start times and deadlines. The proposed algorithms address a fundamental trade-off in dynamic scheduling between the cost of scheduling and the quality of the resulting schedules. The algorithms control the time allocated to scheduling explicitly, in order to obtain good-quality schedules in reasonable times. We show that taking into account the scheduling time is crucial for honoring the deadlines of scheduled real-time tasks. We provide an experimental evaluation of our algorithms via performance comparisons with existing landmark algorithms that were originally designed to address some similar issues. The results of our experiments show that our algorithms outperform the existing techniques in several parameter configurations.

We consider the problem of on-line scheduling of a set of hard real-time tasks in an environment where future task parameters are not known a-priori. First, we derive necessary and sufficient conditions to determine whether a given set of tasks with known parameters is feasible using a set of m processors. Next, we consider two sets of tasks T/sub 0/ and T/sub t/ where T/sub 0/ is the set of tasks that need to be scheduled at time 0 such that any future task set T/sub t/, t>0 can be scheduled with or without disturbing the schedule for T/sub 0/. In this context, we derive necessary and sufficient conditions applicable to the schedule obtained for T/sub 0/ at time 0 such that, any future task set T/sub t/ can be scheduled provided the task set T/sub 0//spl cup/T/sub t/ is feasible using m processors.

Modern Advanced Driver-Assistance Systems (ADAS) combine critical real-time and non-critical best-effort tasks and messages onto an integrated multi-core multi-SoC hardware platform. The real-time safety-critical software tasks have complex interdependencies in the form of end-to-end latency chains featuring, e.g., sensing, processing/sensor fusion, and actuating. The underlying real-time operating systems running on top of the multi-core platform use static cyclic scheduling for the software tasks, while the communication backbone is either realized through PCIe or Time-Sensitive Networking (TSN). In this paper, we address the problem of configuring ADAS platforms for automotive applications, which means deciding the mapping of tasks to processing cores and the scheduling of tasks and messages. Time-critical messages are transmitted in a scheduled manner via the timed-gate mechanism described in IEEE 802.1Qbv according to the pre-computed Gate Control List (GCL) schedule. We study the computation of the assignment of tasks to the available platform CPUs/cores, the static schedule tables for the real-time tasks, as well as the GCLs, such that task and message deadlines, as well as end-to-end task chain latencies, are satisfied. This is an intractable combinatorial optimization problem. As the ADAS platforms and applications become increasingly complex, such problems cannot be optimally solved and require problem-specific heuristics or metaheuristics to determine good quality feasible solutions in a reasonable time. We propose two metaheuristic solutions, a Genetic Algorithm (GA) and one based on Simulated Annealing (SA), both creating static schedule tables for tasks by simulating Earliest Deadline First (EDF) dispatching with different task deadlines and offsets. Furthermore, we use a List Scheduling-based heuristic to create the GCLs in platforms featuring a TSN backbone. We evaluate the proposed solution with real-world and synthetic test cases scaled to fit the future requirements of ADAS systems. The results show that our heuristic strategy can find correct solutions that meet the complex timing and dependency constraints at a higher rate than the related work approaches, i.e., the jitter constraints are satisfied in over 6 times more cases, and the task chain constraints are satisfied in 41% more cases on average. Our method scales well with the growing trend of ADAS platforms.

Scheduling tasks is an essential requirement in most real-time and embedded systems, but leads to unwanted central processing unit (CPU) overheads. The authors present a real-time schedulability algorithm for preemptable, asynchronous and periodic reconfigurable task systems with arbitrary relative deadlines, scheduled on a uniprocessor by an optimal scheduling algorithm based on the earliest deadline first (EDF) principles and on the dynamic reconfiguration. A reconfiguration scenario is assumed to be a dynamic automatic operation allowing addition, removal or update of operating system’s (OS) functional asynchronous tasks. When such a scenario is applied to save the system at the occurrence of hardware-software faults, or to improve its performance, some real-time properties can be violated. The authors propose an intelligent agent-based architecture where a software agent is used to satisfy the user requirements and to respect time constraints. The agent dynamically provides precious technical solutions for users when these constraints are not verified, by removing tasks according to predefined heuristic, or by modifying the worst case execution times (WCETs), periods, and deadlines of tasks in order to meet deadlines and to minimize their response time. They implement the agent to support these services which are applied to a Blackberry Bold 9700 and to a Volvo system and present and discuss the results of experiments.

Although the academic interest in cyclic executives for multitasking in hard real-time systems decreased significantly during the past decades, industry still uses cyclic executives in embedded real-time systems. Unfortunately, contemporary text books hardly address cyclic executives, if at all. There is therefore a need for analysis techniques for these executives.In this document, we consider two basic cyclic executives, i.e. a multi-rate AFAP (as fast as possible) and a multi-rate time-driven AFAP cyclic executive, scheduling a given sequence of independent hard real-time polling tasks in a single-processor system. We present exact analysis for both cyclic executives. Unlike existing approaches, which typically take periodic tasks as a starting point for cyclic executives and focus on schedulability of tasks, we take the schedulability of the system as a starting point, i.e. whether or not the system meets its deadlines. In particular, we do not assume periods and deadlines for tasks.

As the size of data grows rapidly in modern IoT (Internet-of-Things) and CPS (Cyber-Physical System) applications, the memory power consumption of real-time embedded systems increases dramatically. Unlike general-purpose systems where memory consumes about 10% of the CPU power consumption, modern real-time systems have the memory power of 20–50% of CPU power. This is because the memory size of a real-time system should be large enough to accommodate the entire task set, and thus DRAM refresh operations become a major source of power consumption. In this article, we present a new swap scheme for real-time systems, which aims at reducing memory power consumption. To support swap with real-time constraints, we adopt high-speed NVM storage and co-optimize power-savings in CPU and memory. Unlike traditional real-time task models that only consider the executions in CPU, we define an extended task model that characterizes memory and storage paths of tasks as well, and tightly evaluate the worst-case execution time by formulating the overlapped latency between CPU and memory. By optimizing the CPU supply voltage and the memory swap ratio of given task set, our scheme reduces the energy consumption of real-time systems by 31.1% on average under various workload conditions.

For real-time applications, task scheduling is a problem of paramount importance. Several scheduling algorithms were proposed in the literature, starting from static scheduling or cyclic executives which provide very deterministic yet inflexible behaviour, to the so called best-effort scheduling, which facilitates maximum run-time flexibility but allows only probabilistic predictions of run-time performance presenting a non-predictable and nondeterministic solution. Between these two extremes lies fixed priority scheduling algorithms, such as Rate Monotonic, that is not so efficient for real-time purposes but exhibits a predictable approach because scheduling is doing offline and guarantees regarding process deadlines could be obtained using appropriate analysis methods. This paper investigates the use of Rate Monotonic algorithm by making adjustments in order to make it more suitable for real-time applications. The factors that motivate the interest for fixed priority scheduling algorithms such Rate Monotonic when doing with real-time systems lies in its associated analysis that could be oriented in two directions: schedulability analysis and analysis of process interactions. The analyzing process is carried out using a previously implemented framework that allows modelling, simulation and schedulability analysis for a set of real-time system tasks, and some of the results obtained are presented.

Real-time systems are subject to fundamental user requirements, such as correctness of the systems, taking into account timeliness and simultaneity, a high degree of predictability. This means that the scheduling algorithm is an important component of these systems. A scheduling algorithm is used to determine a schedule for a set of tasks so that the task's deadlines and resource requirements are satisfied. The potential speedup of applications has motivated the widespread use of multiprocessors in recent years. In this paper, recent results on multiprocessor real-time scheduling algorithms are reviewed. The review takes the form of an analysis of the problems presented by different application requirements and characteristics. A scheduling algorithm for real-time systems to be implemented on multiprocessors is proposed. This algorithm is appropriate for real-time tasks with the precedence constraints.

In real-time operating systems, timer interrupts are usually used for indicating when a real-time task should be started. Critical sections with interrupts disabled can, however, cause an unacceptable delay in the execution of these tasks. Existing approaches for overcoming this issue either require modifications to many places in the kernel source or introduce a new structural design. In this paper, we propose a simple interrupt management technique for reducing the latency of timer interrupts. The locking mechanism and the timer interrupt handler have been modified so that timer interrupts are not disabled during critical sections, allowing the execution of emergency jobs requested by real-time tasks. We implemented a prototype system in Linux 2.6.20. Experimental results showed that the timer interrupt latency is reduced to 2.2\% of the original Linux kernel and the latency time for executing an emergency real-time job is 27.9$\mu$s in the worst case. Comparing to existing real-time systems, the results showed that proposed technique is efficient enough for a future real-time operating system.

In this paper, we propose a method implementing real-time scheduling in the Unix, a general-purpose operating system (GPOS), by considering the deadline of real-time tasks. Our approach employs a special task called the scheduling daemon, which deals with all the real-time tasks in a system and makes just one task become a ready-to-run state and other sleep states. This causes the Unix scheduler to deal with only one real-time task as a rule, and thus bypasses time sharing-based scheduling strategy of the Unix. Therefore, all the real-time tasks are scheduled by the strategy of the scheduling daemon. We implement the scheduling daemon on the Unix, and build a real-time platform in order that application programmers develop real-time systems more effectively. Moreover, we show the superiority of our approach through extensive experiments.

This paper presents a novel design of a coprocessor that performs hardware-accelerated task scheduling for embedded real-time systems consisting of mixed-criticality real-time tasks. The proposed solution is based on the Robust Earliest Deadline (RED) algorithm and previously developed hardware architectures used for scheduling of real-time tasks. Thanks to the HW implementation of the scheduler in the form of a coprocessor, the scheduler operations (i.e., instructions) are always completed in two clock cycles regardless of the actual or even maximum task amount within the system. The proposed scheduler was verified using simplified version of UVM and applying billions of randomly generated instructions as inputs to the scheduler. Chip area costs are evaluated by synthesis for Intel FPGA Cyclone V and for 28-nm TSMC ASIC. Three versions of real-time task schedulers were compared: EDF-based scheduler designed for hard real-time tasks only, GED-based scheduler and the proposed RED-based scheduler, which is suitable for tasks of various criticalities. According to the synthesis results, the RED-based scheduler consumes LUTs and occupies larger chip area than the original EDF-based scheduler with equivalent parameters used. However, the RED-based scheduler handles variations of task execution times better, achieves higher CPU utilization and can be used for the scheduling of hard real-time, soft real-time and nonreal-time tasks combined in one system, which is not possible with the former algorithms.

In this paper, we propose a duplication-based algorithm (IDSA) for the integrated scheduling of precedence related real-time tasks with hard and soft deadlines on a set of heterogeneous multiprocessors. We employ a priority-based scheme in which the hard subtasks are always allotted a higher priority as compared to the soft subtasks. IDSA utilizes selective subtask duplication that enables some subtasks to have earlier start times, which results in an increased number of subtasks (and hence task sets) finishing before their deadlines, thereby increasing the schedulability of a real-time application. Our algorithm is also shown to be capable of scheduling a real-time application even if the available number of processors is less than the required number of processors. Based on extensive simulation results, we observe that IDSA offers better success ratio as compared to the existing algorithms in the literature when communication is a dominant factor in the system.