Secure and Efficient RNS Software Implementation for Elliptic Curve Cryptography

Modern-day embedded systems such as IoT and other smart electronic devices are vulnerable to side-channel analysis (SCA) attacks due to their ease of physical access to devices. Hardware implementation should be secured with SCA countermeasures to protect data from such attacks. This dissertation proposes a residue number system (RNS)-based logic to protect against power side-channel attacks. By converting the different input binary values into similar bit encodings for the shares, the RNS logic enables side-channel privacy and cryptographic privacy. In the study, this trait is also recorded as a symmetry measure. The side-channel resistance of RNS secure logic is assessed both conceptually and practically. An analytical metric is developed to quantify the conditional probability of the input bit state given the residue state visible to the adversary but derived from hidden cryptographic secrets. Transition probability, normalized variance, and Kullback–Leibler (KL) divergence serve as side-channel metrics in this study. The results show that our RNS secure logic provides better resistance against high-order side-channel attacks regarding power distribution uniformity and success rates of machine learning (ML)-based power side-channel attacks. We performed SPICE simulations on Montgomery modular multiplication and Arithmetic-style multiplication using the FreePDK 45nm technology library. Another significant and developing issue is the need for security analysis on the EDA tool flow. In this work, the values and topologies of the decoupling capacitance included in an on-chip power distribution network for side-channel resistance are investigated. We demonstrate that an on-chip power distribution network with decoupling capacitance prevents power side-channel attacks. The proposed architecture distributes multiple decoupling capacitances along the power lines to avoid data leakage from sensitive logic blocks. The impact of decoupling capacitance on power side-channel resistance is studied using grid-style and tree-style power distribution networks. Research employs a unique, approximate approach for extracting the feature vector from the switching current of the internal logic blocks. The side-channel resistance is quantified by the success rates of machine learning classifiers such as Naive Bayes (NB), Linear Discriminant Analysis (LDA), Quadratic Discriminant Analysis (QDA), and Support Vector Machine (SVM).

The Residue Number System (RNS) is a numeral representation enabling for more efficient addition and multiplication implementations. However, due its non-positional nature, modular reductions, required for example by Elliptic Curve (EC) Cryptography (ECC), become costlier. Traditional approaches to RNS modular reduction resort to the Montgomery algorithm, underpinned by large basis extensions. Recently, Hybrid-Positional Residue Number Systems (HPRs) have been proposed, providing a trade-off between the efficiency of RNS and the flexibility of positional number representations. Numbers are represented in a positional representation with the coefficients represented in RNS. By crafting primes of a special form, the complexity of reductions modulo those primes is mitigated, relying on extensions of smaller bases. Due to the need of crafting special primes, this approach is not directly extensible to group operations over currently standardised elliptic curves. In this paper, the Hybrid-Polynomial Residue Number System (HyPoRes) is proposed, enabling for improved modular reductions for any prime. Experimental results show that the modular reduction of HyPoRes, although at most 1.4 times slower than HPR for HPR-crafted primes, is up to 1.4 times faster than a generic RNS approach for primes of ECC standards.

Security in embedded systems is of critical importance since most of our secure transactions are currently made via credit cards or mobile phones. Power analysis-based side channel attacks have been proved as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks on public key cryptographic algorithms, such as elliptic curve cryptography, mostly in software, hinder performance and repeatedly attacked using improved techniques. To protect these public key ciphers from both simple power analysis and differential power analysis, as a hardware solution, we propose to take advantage of the inherent parallelisation capability in multi-modulo residue number systems (RNS) architectures to obfuscate the secure information. Random selection of moduli is proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, although still providing all the benefits of RNS. In this study, the authors show that differential power analysis, cross correlation analysis and correlation power analysis for a simple binary double-and-add operation are thwarted using their solution.

An elliptic curve point multiplier (ECPM) is the main part of all elliptic curve cryptography (ECC) systems and its performance is decisive for the performance of the overall cryptosystem. A VLSI residue number system (RNS) architecture of an ECPM is presented in this paper. In the proposed approach, the necessary mathematical conditions that need to be satisfied, in order to replace typical finite field circuits with RNS ones, are investigated. It is shown that such an application is feasible and that it leads to a significant improvement in the execution time of a scalar point multiplication.

The additional information (side effects) in Elliptic Curve Cryptography (ECC) hardware can be used to attack cryptographic systems. Additional information related to time, power consumption and electromagnetic radiation. Side channel attacks have been done with SPA (Simple Power Analysis), DPA (Differential Power Analysis), SEMA (Simple Electromagnetic Analysis) and DEMA (Differential Electromagnetic Analysis). Some scalar multiplication algorithm can be used to countermeasure SPA attack on elliptic curve cryptography. In this study, conducted experiments side-channel attacks ECC hardware implementations use binary algorithms by observing power consumption of ECC processor on FPGA. Experimental of side-channel attack is conducted to guess the secret key for data encryption and decryption by looking at the physical differences on hardware side effects. In this study, side-channel attack experimental is successful 100% get the key by analyzing of power consumption ECC processor.

Power analysis attacks are one of the most common Side-Channel Attacks (SCAs), proven to be extremely successful even on protected embedded devices. This paper proposes the use of a Residue Number System (RNS) architecture with randomly permuted moduli sets to implement the Double-and-Add computation, which is proven as the most susceptible operation in Elliptic Curve Cryptography (ECC). The proposed solution randomly permutes the moduli sets, allowing randomized power traces, significantly removing the correlation between the power dissipation and the secret key and eliminating the need for the intermediate conversion to binary required in the state-of-the-art. Architectures obtained for a 90nm standard cell technology suggest that a significant power analysis resistance is achieved for the Double-and-Add circuitry, incurring an extra performance cost of 3 times compared to the related state-of-the-art.

Public‐key cryptosystems such as elliptic curve cryptography (ECC) and Rivest–Shamir–Adleman (RSA) are widely used for data security in computing systems. ECC provides a high level of security with a much smaller key than RSA, which makes ECC a preferred choice in many applications. This study proposes a multi‐key ECC based on the residue number system. The proposed architecture employees deep pipelining to allow the concurrent encryption of 21 keys. The proposed architectures are implemented on two different field programmable gate array (FPGA) platforms and results are compared with existing ECC architectures. The proposed implementation on Virtex‐7 FPGA achieves a throughput of 1816 kbps at a clock frequency of 73 MHz.

Embedded systems are increasingly providing secure functionalities, which often rely on some dedicated hardware for symmetric and public-key cryptography. When resources are limited, elliptic curve cryptography (ECC) may be chosen instead of the more widely known RSA, which needs much longer keys for the same security level. However, ECC may be vulnerable, as any other cryptographic implementation, to side channel analysis, which may reveal secret information by analyzing collateral sources of information, such as power consumption. Countermeasures must be thus adopted at the design level, in order to ensure robust and secure operation of the device. We propose here a new scalar multiplication algorithm on an elliptic curve, based on a novel randomized window method. This design is protected against side channel attacks (Timing, Simple and Differential Power Analysis) and it is implemented over prime fields, but it can be applied to binary fields as well. In order to evaluate this countermeasure, we provide its costs, and an estimation of the additional entropy added to the computation against side channels attacks.

Modular multiplication (MM) based on the residue number system (RNS) is a widely researched area due to the fast arithmetic operations in the RNS. The major drawback of the RNS based MM architectures is their large area because each arithmetic operation is followed by a modular reduction. In this work, the number of modular reductions is reduced and instead the wordlength of some operations is increased to accommodate the intermediate results. The proposed scheme greatly reduces the number of multipliers and achieves a 55% reduction in the hardware complexity. Moreover the delay of the proposed architecture is also significantly lower than the reference architecture.

In this work, we present a systematic study of Side-Channel Attacks (SCA) and Fault Injection Attacks (FIA) on structured lattice-based schemes, with main focus on Kyber Key Encapsulation Mechanism (KEM) and Dilithium signature scheme, which are leading candidates in the NIST standardization process for Post-Quantum Cryptography (PQC). Through our study, we attempt to understand the underlying similarities and differences between the existing attacks while classifying them into different categories. Given the wide variety of reported attacks, simultaneous protection against all the attacks requires to implement customized protections/countermeasures for both Kyber and Dilithium. We therefore present a range of customized countermeasures, capable of providing defenses/mitigations against existing SCA/FIA, and incorporate several SCA and FIA countermeasures within a single design of Kyber and Dilithium. Among the several countermeasures discussed in this work, we present novel countermeasures that offer simultaneous protection against several SCA- and FIA-based chosen-ciphertext attacks for Kyber KEM. We implement the presented countermeasures within two well-known public software libraries for PQC: (1) pqm4 library for the ARM Cortex-M4-based microcontroller and (2) liboqs library for the Raspberry Pi 3 Model B Plus based on the ARM Cortex-A53 processor. Our performance evaluation reveals that the presented custom countermeasures incur reasonable performance overheads on both the evaluated embedded platforms. We therefore believe our work argues for usage of custom countermeasures within real-world implementations of lattice-based schemes, either in a standalone manner or as reinforcements to generic countermeasures such as masking.

The paper presents algorithms for the generation of Residue Number System (RNS) triples with $SQ=2^{k}-1$ and quadruples with $SQ=2^{k}$ for some k. Triples and quadruples allow us to design efficient hardware implementations of non-modular operations in RNS such as division, sign detection, comparison of numbers, reverse conversion with using of a diagonal function from requiring division with the remainder by the diagonal module SQ. Division with a remainder in the general case is the most complex arithmetic operation in computer technology. However, the consideration of special cases can significantly simplify this operation and increase the efficiency of hardware implementation. We show that there are 5573 good RNS triples (2301 even and 2372 odd) with elements less than 10 000, as the values of SQ vary from $2^{5}-1$ to $2^{27}-1$ . In contrast, RNS quadruples with $SQ=2^{k}$ seem to be quite rare. Restricting our search to sums of the elements in a quadruple less than 4000 we find that exactly 31 such quadruples exist. Their values of SQ vary between 220 and 230 with always even exponent. We suggest the measure of RNS balance and find perfectly balanced RNS among triples according to this measure. We demonstrate the advantages of more balanced quadruples by means of hardware implementation.

We present a high-speed public-key cryptoprocessor that exploits three-level parallelism in Elliptic Curve Cryptography (ECC) over GF(2 n ). The proposed cryptoprocessor employs a Parallelized Modular Arithmetic Logic Unit (P-MALU) that exploits two types of different parallelism for accelerating modular operations. The sequence of scalar multiplications is also accelerated by exploiting Instruction-Level Parallelism (ILP) and processing multiple P-MALU instructions in parallel. The system is programmable and hence independent of the type of the elliptic curves and scalar multiplication algorithms. The synthesis results show that scalar multiplication of ECC over GF(2163) on a generic curve can be computed in 20 and 16 μs respectively for the binary NAF (Non-Adjacent Form) and the Montgomery method. The performance can be accelerated furthermore on a Koblitz curve and reach scalar multiplication of 12 μs with the TNAF (τ-adic NAF) method. This fast performance allows us to perform over 80,000 scalar multiplications per second and to enhance security in wireless mobile applications.

The Montgomery Ladder is widely used for implementing the scalar multiplication in elliptic curve cryptographic designs. This algorithm is efficient and provides a natural robustness against (simple) side-channel attacks. Previous works however showed that implementations of the Montgomery Ladder using Lopez-Dahab projective coordinates easily leak the value of the most significant bits of the secret scalar, which led to a full key recovery in an attack known as LadderLeak [3]. In light of such leakage, we analyse further popular methods for implementing the Montgomery Ladder. We first consider open source software implementations of the X25519 protocol which implement the Montgomery Ladder based on the ladderstep algorithm from Düll et al. [15]. We confirm via power measurements that these implementations also easily leak the most significant scalar bits, even when implementing Z-coordinate randomisations. We thus propose simple modifications of the algorithm and its handling of the most significant bits and show the effectiveness of our modifications via experimental results. Particularly, our re-designs of the algorithm do not incurring significant efficiency penalties. As a second case study, we consider open source hardware implementations of the Montgomery Ladder based on the complete addition formulas for prime order elliptic curves, where we observe the exact same leakage. As we explain, the most significant bits in implementations of the complete addition formulas can be protected in an analogous way as we do for Curve25519 in our first case study.KeywordsECCMontgomery LadderCurve25519Complete addition formulasSide-channel analysis

Modular adders are fundamental arithmetic components that are employed in residue number system (RNS) based digital signal processing (DSP) systems. They are widely used in modular multipliers, residue to binary converters and in implementing other arithmetic operations such as scaling. In addition, increasing operating frequencies, as well as a growing demand for portable electronics, have brought power reduction to the forefront of modern design methodologies. Thus, the design of power efficient modular adders is of great significance if RNS circuits are to be utilized in future DSP systems. We propose a new modular adder that is based on the ELM addition algorithm. VLSI implementations using 0.13 /spl mu/m standard-cell technology show that the proposed architecture not only exhibits power efficiency, but also delay /spl times/ area efficiency when compared to existing modular adder designs in the literature.

Residue number system (RNS) representations that contain redundant moduli have been extensively studied with regard to their error checking properties. A second form of redundancy in RNS, that of redundant residues, has been applied in certain application contexts to gain speed and cost benefits. Such applications are developed in an ad hoc manner and there does not exist a theoretical framework for the latter variety of redundant RNS. We develop a theory of RNS representations with redundant residues and show how representation parameters affect the speed and complexity of various arithmetic operations. The theory parallels that of redundant signed-digit representations in that at issue are choice of 'residue sets' (akin to digit sets), encoding of residue sets, conversions between residue sets with different degrees of redundancy, including none, and algorithms for arithmetic on redundant-residue operands.