Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks

A new class of spin-transfer torque magnetic random access memory (STT-MRAM) is discussed, in which writing is achieved using thermally initiated magnonic current pulses as an alternative to conventional electric current pulses. The magnonic pulses are used to destabilize the magnetic free layer from its initial direction, and are followed immediately by a bipolar electric current exerting conventional spin-transfer torque on the free layer. The combination of thermal and electric currents greatly reduces switching errors, and simultaneously reduces the electric switching current density by more than an order of magnitude as compared to conventional STT-MRAM. The energy efficiency of several possible electro-thermal circuit designs have been analyzed numerically. As compared to STT-MRAM with perpendicular magnetic anisotropy, magnonic STT-MRAM reduces the overall switching energy by almost 80%. Furthermore, the lower electric current density allows the use of thicker tunnel barriers, which should result in higher tunneling magneto-resistance and improved tunnel barrier reliability. The combination of lower power, improved reliability, higher integration density, and larger read margin make magnonic STT-MRAM a promising choice for future non-volatile storage.

Spin-transfer torque magnetic random access memory (STT-RAM) technology has emerged as a potential replacement of SRAM in cache design, especially for building large-scale and energy-efficient last level caches. Compared with single-level cell (SLC), multi-level cell (MLC) STT-RAM is expected to double cache capacity and increase system performance. However, the two-step read/write access schemes incur considerable energy consumption and performance degradation. In this paper, we propose two techniques using data compression to optimize MLC STT-RAM cache design. The first technique tries to compress a cache line and fit it into only the soft-bit region of the cells, so that reading or writing this cache line takes only one step which is fast and energy-efficient. We introduce a second technique to increase the cache capacity by enabling the left hard-bit region to store another compressed cache line, which can improve the system performance for memory intensive workloads. The experimental results show that, compared with a conventional MLC STT-RAM last level cache design, our overhead minimized technique reduces the dynamic energy consumption by 38.2% on average with the same system performance, and our capacity augmented technique boosts the system performance by 6.1% with 19.2% dynamic energy saving on average, across the evaluated multi-programmed benchmarks.

The read reliability of spin-transfer torque magnetic random access memory (STT-MRAM) is greatly hindered by a low sensing margin as a result of a small tunneling magneto-resistance ratio (TMR). Although the new generation of perpendicular anisotropy spin-orbit torque (SOT)-MRAM offers faster access speed and longer lifetime than STT-MRAM, its read performance is not improved or even deteriorated because of the additional resistance of SOT channel in the read path. In this letter, we propose two novel cell structures of SOT-MRAM, which consist of one/two transistors, two diodes, and two magnetic tunnel junctions (1T2D2MTJ/2T2D2MTJ) on a shared U-shaped anti-ferromagnet layer, enabling a self-referencing scheme. Thanks to the bent current channel, the opposite direction of the SOT current below the free layers can one-step switch different data states in compatibility with the existing fabrication process of SOT-MRAM. Combined with the 28 nm tech node and Verilog-A MTJ compact model, the simulation results show that our proposed MRAM cell significantly improves sensing margin and bit error rate over the conventional 2T1M cell, which is expected to become a high read performance solution.

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high write energy consumption. This paper proposes a cache management technique called Proactive Invalidation (PROI) that proactively invalidates dead blocks in advance to enable fast writes in the STT-MRAM caches. Experimental evaluation shows that the proposed technique improves performance by 14% on average compared to the baseline STT-MRAM cache. This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation. Experimental results demonstrate that the total energy consumption of the STT-MRAM cache with PROI is only 1.8% higher than the baseline when PROI is applied with PIDE and NPW.

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

This paper presents Cryo-SIMPLY, a reliable smart material implication (SIMPLY) operating at cryogenic conditions (77 K). The assessment considers SIMPLY schemes based on spin-transfer torque magnetic random access memory (STT-MRAM) technology with single-barrier magnetic tunnel junction (SMTJ) and double-barrier magnetic tunnel junction (DMTJ). Our study relies on a temperature-aware macrospin-based Verilog-A compact model for MTJ devices and a 65 nm commercial process design kit (PDK) calibrated down to 77 K under silicon measurements. The DMTJ-based SIMPLY demonstrates a significant improvement in read margin at 77 K, overcoming the conventional SIMPLY scheme at room temperature (300 K) by approximately 2.3 X. When implementing logic operations with the SIMPLY scheme operating at 77 K, the DMTJ-based scheme assures energy savings of about 69%, as compared to its SMTJ-based counterpart operating at 77 K. Overall, our results prove that the SIMPLY scheme at cryogenic conditions is a promising solution for reliable and energy-efficient logic-in-memory (LIM) architectures.

Spin-transfer torque magnetic random access memory (STT-MRAM) requires large interfacial perpendicular magnetic anisotropy (iPMA) to be maintained even after many microfabrication steps. The data retention of STT-MRAM depends on the quality of the interface between the ferromagnetic layer and the insulating layer in magnetic tunnel junction (MTJ). We have investigated the effects of the grain boundary (GB) in the MgO layer on the iPMA using first-principles calculations. The results show that the iPMA is reduced by the presence of GBs, even though some iPMA remains. This is explained by a decrease in the peak of density of states (DOS) just above the Fermi energy, and that the DOS at high energy is increased in the down spin channel for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${d}_{xz}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$d_{yz}$ </tex-math></inline-formula> orbitals. Moreover, we found that the bond structure of Fe-d orbitals around the GB is a key factor controlling the iPMA, in addition to the well-known role of interfacial Fe–O bonds.

Thin films with perpendicular magnetic anisotropy (PMA) have been widely studied for perpendicular recording media since the middle of the 1970s when Prof. Iwasaki suggested this approach [1]. Since them, a great effort has been done by the research community for the use of this kind of nanostructures with PMA in other technological applications such as in high-density spin-transfer torque magnetic random access memories (STT-MRAM) [2], skyrmion-based devices [3] or even in synthetic antiferromagnets for biomedical applications [4].PMA in thin films can be usually achieved through different strategies such as by using materials with large magnetocrystalline anisotropy energy [5] as well as multilayer thin films with high surface anisotropy energy contributions [6]. Regarding the last alternative, Ikeda et al. [2] demonstrated in 2010 that amorphous CoFeB ultrathin films can show PMA and it is supported by the CoFeB/MgO interfacial anisotropy contribution. Since then, the development of non-magnetic/ferromagnetic superlattices with PMA, using CoFeB alloys as the ferromagnetic element, has received great attention. In particular, PMA in CoFeB/Pd was first demonstrated in bilayers by Fowley et al. [7] as well as in multilayers by Jung et al. [8]. Literature has reported that the effective anisotropy energy depends on the thickness of magnetic (tCoFeB) and non-magnetic (tPd) layers as well as on the number of bilayers (N).In this work, the dynamical response of [CoFeB (tCoFeB) / Pd (10 Å)]5 multilayered ultrathin films (1 Å ≤ tCoFeB ≤ 5 Å) were studied by using two complementary methods: broadband ferromagnetic resonance (Figure 1 a) and time-resolved magneto-optical Kerr effect (Figure 1 b). The perpendicular magnetization was confirmed for multilayers with tCoFeB ≤ 4 Å, while magnetization became in-plane oriented for tCoFeB ≥ 5 Å. This behaviour was explained by considering competing contributions from surface and magnetoelastic anisotropies. In addition, we have observed that the effective damping parameter is reduced with increasing tCoFeB (Figure 1 c), and the lower parameter, αeff ≈ (0.019 ± 0.001), was determined for the multilayer with 4 Å CoFeB thickness. We have suggested that for tCoFeB ≥ 4 Å the layer is continuous and the main contribution to effective damping is coming from spin-pumping when for lower thicknesses αeff is dominated by two-magnon scattering.Afterwards, we have studied the magnetic behaviour of ultrathin [CoFeB(tCoFeB)/Pd(10 Å)]N films. Intending to ensure that the system shows PMA, tCoFeB (3 or 4 Å) was fixed, while the number of bilayers (N) was ranged from 3 to 15. We observed that our samples show PMA and it is generally improved with N. In addition, we studied the dependence of αeff with the number of CoFeB/Pd repeats (N). Up today, literature in superlattices with PMA reported that αeff is proportional, inversely proportional or even, independent of N [9]. Therefore, the reported relationship between the damping parameter and N in superlattices with PMA is still unclear. We show that the evolution of αeff with N shows a complex behaviour that we have correlated with the magnetization process: larger αeff for samples with square hysteresis loops while αeff is independent of N for samples with bow-tie-shaped hysteresis loops. **

Resonance spin-transfer torque in ferromagnetic/normal-metal/ferromagnetic spin-valve structure of topological insulators

Thermodynamic stability, magnetism and half-metallicity of various (100) surfaces of Heusler alloy Ti2FeSn

In spin-transfer torque magnetic random access memory (STT-MRAM), retention-, write-, and read-failures negatively impact the memory yield and density. In this paper, we jointly consider device-circuit-architecture layers to implement high-density STT-MRAM array while meeting the target yield requirement. Different types of magnetic tunnel junctions are considered at the device level, and error correcting codes (ECCs) in conjunction with invert-coding are employed as an architectural solution. Through cross-layer interactions, we present a design methodology to optimize bit-cell area while satisfying the target yield and energy consumption under process variation. Furthermore, we explore the use of invert-coding along with ECC in order to achieve higher memory density than that obtained using ECC alone. Our proposed technique can improve memory density further by proper selection of thermal stability factor based upon two observations: 1) invert-coding can fix multiple write/read failures with small storage overhead and 2) as thermal stability factor increases, retention-failure probability exponentially decreases, and thus, simple ECC is good enough for retention failure correction.

In the rapidly evolving landscape of modern electronics, memory devices and circuits play a pivotal role in determining system performance, energy efficiency, and scalability. Traditional memory technologies, such as Dynamic Random Access Memory (DRAM) and NAND flash, face challenges related to scaling limits, latency, power consumption, and endurance, particularly as demands for faster and more efficient data storage grow. Emerging non-volatile memory (NVM) technologies like Resistive Random Access Memory (ReRAM), Phase-Change Memory (PCM), and Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) offer potential solutions to these challenges, but their combination into existing systems poses design and manufacturing hurdles. The primary problem lies in balancing storage performance with power efficiency while ensuring scalability for advanced applications such as artificial intelligence (AI), Internet of Things (IoT), and high-performance computing (HPC). Innovations in circuit design, including advanced error-correction mechanisms, adaptive voltage scaling, and low-power architectures, are critical in enhancing the overall performance of memory systems. This study employs a hybrid approach, combining novel circuit design techniques with the combination of emerging NVM technologies. Simulations were performed to evaluate the performance metrics, including write latency, energy consumption, and endurance. Results show that ReRAM-based memory designs achieved a 35% reduction in write latency and a 50% improvement in energy efficiency compared to traditional DRAM, while PCM demonstrated superior endurance with up to 10^8 write cycles. Furthermore, STT-MRAM circuits showed promise with a 40% reduction in standby power consumption. These advancements in memory circuits and devices highlight the potential for significant improvements in storage performance and efficiency, addressing the growing needs of modern electronic systems and paving the way for future innovations in computing.

In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. Computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array can be activated simultaneously to perform bitwise logic operations, such as OR/NOR and AND/NAND. In addition, with technology scaling down, STT-MRAM suffers from high sensitivity to process variation, which results in more device mismatch in a sense circuit. Additionally, the negative bias temperature instability (NBTI) seriously affects the life of PMOS transistors used in a sense circuit. In this paper, a high-reliability sense amplifier for computing in-memory with STT-MRAM is proposed. By using two self-enabled switching transistors, the proposed sense amplifier not only can decrease the NBTI effect on PMOS transistors but also can achieve a low sensing error rate. Using a CMOS 40[Formula: see text]nm design-kit and an accurate compact model of the STT magnetic tunnel junction (MTJ), mixed transient and statistical simulations have been present to demonstrate the functionality and performance of the proposed circuits.

Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate for next generation memory as it is non-volatile, fast, and has unlimited endurance. Another important aspect of STT-MRAM is that its core component, the nanoscale magnetic tunneling junction (MTJ), is thought to be radiation hard, making it attractive for space and nuclear technology applications. However, studies on the effects of ionizing radiation on the STT-MRAM writing process are lacking for MTJs with perpendicular magnetic anisotropy (pMTJs) required for scalable applications. Particularly, the question of the impact of extreme total ionizing dose on perpendicular magnetic anisotropy, which plays a crucial role on thermal stability and critical writing current, remains open. Here we report measurements of the impact of high doses of gamma and neutron radiation on nanoscale pMTJs used in STT-MRAM. We characterize the tunneling magnetoresistance, the magnetic field switching, and the current-induced switching before and after irradiation. Our results demonstrate that all these key properties of nanoscale MTJs relevant to STT-MRAM applications are robust against ionizing radiation. Additionally, we perform experiments on thermally driven stochastic switching in the gamma ray environment. These results indicate that nanoscale MTJs are promising building blocks for radiation-hard non-von Neumann computing.

The Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been identified, by the International Technology Roadmap for Semiconductors (ITRS), as one of the most promising emerging technology. Different works handled the retention and reliability of STT-MRAM. However, to the best of our knowledge, the impact of a pulsed laser beam on STT-MRAM reliability and security has not been investigated so far as proposed in this paper. Since STT-MRAM are Back-end Of Line devices, we exposed the bit cells from the front-side to a 1064 nm wavelength laser pulse. The devices are electrically characterized (switching conditions between the two logical states) before and after the laser irradiation. The main result of this study is the demonstration of a resistance switching from Anti-Parallel (AP) to Parallel (P) state after the laser irradiation. That is how data integrity was altered by this irradiation, flipping the bit stored in this memory.