Security Measures Against a Rogue Network-on-Chip

With technology scaling, Multiprocessor System on Chip (MPSoC) which consist of multiple processors connected via a Network on Chip (NoC) have become prevalent. Applications are mapped to MPSoC's by representing it in the form of a task graph. Task scheduling involves mapping task to processor cores so as to meet the deadline. For a given deadline, slack at each node is defined by the amount of time by which a task execution can be delayed without missing the deadline. With increase in the number of cores and high application parallelism, NoC is becoming a bottleneck due to the presence of large number of concurrent communications. Increasing network resources (links and routers) reduces the communication time but the area and power goes up. In this paper we present an application aware heuristic to synthesize a minimal network connecting a set of cores in an MPSoC in the presence of hard deadlines. Our approach is based on modeling communication between a pair of processors as tasks known as “Comtasks”. The network is generated by “scheduling” these comtasks onto a set of routers so as to obtain a network with minimum area which fills up the available slack. Moreover, we also identify the set of overlapping comtasks and generate a minimal network to allow the maximum set of overlapping comtasks to execute concurrently. We compared our approach with a greedy network generation heuristic and the results show 80% benefit in the router area.

Multi-Processors System-on-Chip (MPSoCs) have emerged as the enabler technology for new computational paradigms such as Internet-of-Things (IoT) and Machine Learning. Network-on-Chip (NoC) communication paradigm has been adopted in several commercial MPSoCs as an effective solution for mitigating the communication bottleneck. The widespread deployment of such MPSoCs and their utilization in critical and sensitive applications, turns security a key requirement. However, the integration of security into MPSoCs is challenging. The growing complexity and high hyper-connectivity to external networks expose MPSoC to Malware infection and code injection attacks. Isolation of tasks to manage the ever-changing and strict mixed-criticality MPSoC operation is mandatory. Hardware-based firewalls are an effective protection technique to mitigate attacks to MPSoCs. However, the fast reconfiguration of these firewalls impose a huge performance degradation, prohibitive for critical applications. To this end, this paper proposes a lightweight broadcasting mechanism for firewall reconfiguration in NoC-based MPSoC. Our solution supports efficient and secure creation of dynamic security zones in the MPSoC through the communication management while avoiding deadlocks. Results show that our approach decreases the security reconfiguration process by a factor of 7.5 on average when compared to the state of the art approaches, while imposing negligible area overhead.

As there is a rapid growth in use of consumer embedded products from past decade, new tendencies forecast highly the usage of heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. As MPSoCs are made up of hundreds of cores, Intercommunication requirements will not be feasible using a single shared bus or a hierarchy of buses due to their poor scalability with system size, and the different components are designed by various vendors, their shared bandwidth between all the attached cores and the energy efficiency requirements of final products. To overcome the above said problems of scalability and complexity, Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MPSoCs connected by means of general-purpose communication architectures. However, the development of application-specific NoCs for MPSoCs is a complex engineering process that involves the definition of suitable protocols and topologies of switches, and which demands adequate design flows to minimize design time and effort. In fact, the development of suitable high-level design and synthesis tools for NoC-based interconnects is a key element to benefit from NoC-based interconnects design in nanometer-scale CMOS technologies. This paper presents the design and implementation of FPGA based Network on chip (NoC) which is scalable packet switched architecture with advanced Networking functionalities such as store & forward transmission, error management, power management and security. All these features are built on basic NI core, which includes data packetization/depacketisation, frequency conversion, data size conversion and conversion of protocols with limited circuit complexity and cost.

The design of a Multiprocessor System-on-Chip (MPSoC) is a complex task, including steps as application development, platform configuration, code generation, task mapping onto the platform and debugging. An integrated environment covering most of these steps is a gap in the literature. The present work first details an MPSoC architecture, which supports the execution of distributed applications, including an operating system enabling multitask execution at each processing element. The MPSoC is heterogeneous, due to the support to different processor architectures. Then, a framework able to cover the design steps previously mentioned is presented. The framework enables the design space exploration for applications to be executed in the MPSoC, varying for example the number and type of processors, the memory size, the task mapping. Results demonstrate the correct operation for different MPSoC configurations, generated from the proposed framework. Such open-source framework enables the research community to investigate new subjects related to MPSoC and Network on Chip (NoC) design, as well as evaluate distributed applications in a multiprocessor environment.

Since 2001, there have been a myriad of papers on systematic analysis of multi-processor system on chip (MPSoC) and network on chip (NoC). Nevertheless, we only have a few of their practical application. Till now, main interest of researchers has been to adapt NoC to the communication intensive multimedia system like H.263. However, this paper attempts to expand the domain of NoC platform to one of the wireless security algorithms (TKIP), because its inter-component transaction pattern shows considerable characteristic for NoC. This paper consists of the explanation on operational sequence of the algorithm in chosen architecture and the brief illustration of important composing NoC blocks (Network Interface, Router).

Over the years, system on chip (SoC) designs have evolved extensively sophisticated in order to fulfil the need of increasing complexity of running applications driven by the advancement of VLSI technology. The next generation multiprocessor system on chip (MPSoC) integrates hundreds of processing elements on a single chip, expected to achieve high performance, low latency, and low-power consumption. Tiled chip multicore processors (TCMP) with network on chip (NoC) have become a foundation for the computation critical embedded and real-time systems. Faster time-to-market restraint and business competition compelled manufacturers to look for the prospects of manufacturing SoCs integrated with various third party intellectual property (3PIP). Usage of 3PIP gave rise to exploit the underlying interconnect while adding some unwanted malicious circuit known as hardware trojan (HT), making NoC vulnerable to get attacked. A tiniest manipulation of any communication attribute by HT can degrade the overall behaviour of the system significantly while impacting NoC performance metrics. In this paper, we present one of such study considering HT malign behaviour of manipulating the output port of each incoming flit from specific ports once genuine route computation takes place and re-directs all to one port causing disruption in tile communication.The proposed HT is intermittent in nature and activates for few cycles. We study the behaviour of proposed confluence attack and analyze its impact over network level. The empirical evaluation exhibits the misbehaviour of the packet communication in terms of wrong usage of VCs and extra hop distance overhead. To validate the proposed work, various performance metrics like buffer utilization, virtual channel utilization, number of flits processed, link utilization, and the like are analyzed. We also show that such HTs are difficult to detect due to marginal increase at malicious port traffic leaving no trace of malicious conduct.

Multi-processor System-on-Chip (MPSoC) architectures in future will be imple- mented in less than 50 nm technology and include tens to hundreds of process- ing element blocks operating in the multi-GHz range. The on-chip interconnec- tion network will be a key factor in determining the performance and power consumption of these multi-core devices. Packet switched interconnection net- works or Network-on-Chip (NoC) has emerged as an attractive alternative to tra- ditional bus-based architectures for satisfying the communication requirements of these MPSoC architectures. The key challenge in NoC design is to produce a complex, high performance and low energy architecture under tight time to market requirements. The NoC architectures would support the communication demands of hundreds of cores under stringent performance constraints. In addi- tion to the complexity, the NoC designers would also have to contend with the physical challenges of design in nanoscale technologies. The NoC design prob- lem would entail a joint optimization of the system-level floorplan and power consumption of the network. All these factors coupled with the requirement for short turn around times raises the need for an intellectual property (IP) re-use methodology that is well supported with design and optimization techniques, and performance evaluation models. This chapter introduces the concept of NoC and presents the various elements of the IP-based system-level methodology required for its design.

Multiprocessor Systems-on-Chip (MPSoCs) are a promising solution to fulfill the requirements of high performance computing applications, such as image processing or bioinformatics. Many different MPSoC architectures are introduced by industry and academics, such as Intel's Single Cloud Computer (SCC) or IBM's Cell. To achieve a high efficiency on such MPSoCs a high computing performance in the processing elements (PE) is not the only parameter. The bandwidth of the memory and especially the on-chip communication infrastructure are extremely important to achieve the requirements of the applications. Furthermore, for embedded System-on-Chip solutions, flexibility is extremely important for providing a good tradeoff between performance and power consumption. Especially, for general purpose MPSoCs, designed for a wide range of applications with different communication demands, this flexibility is essential for a good energy efficiency. A simple bus or Network-on-Chip (NoC) with fixed bandwidth and communication paradigm is not sufficient in this varying application scenario and its design space. In this paper novel features for the heterogeneous and runtime adaptive Star-Wheels Network-on-Chip are presented. This Network-on-Chip is used within a runtime adaptive MPSoC, which enables to tailor processors and accelerators to the requirements of the applications. For optimizing the Star-Wheels Network-on-Chip and its communication protocol at runtime to the application requirement the following novel features have been added: the combination of the circuit- and the packet-switched communication paradigm and an algorithm-based placement of the processing elements within the NoC. The integration of the novel algorithm into the design methodology and the exploitation of the novel features within the special purpose runtime operating system of a runtime adaptive MPSoC are also introduced.

With increasing core counts ushering in power-constrained 3-D multiprocessor system-on-chips (MPSoCs), optimizing communication power dissipated by the 3-D network-on-chip (NoC) fabric is critical. At the same time, with increased power densities in 3-D ICs, problems of IR drops in the power delivery network (PDN) as well as thermal hot spots on the 3-D die are becoming very severe. Even though the PDN and NoC design goals are nonoverlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider the design of the PDN, while designing NoCs. Moreover, for each new configuration of computation core and communication mapping on an MPSoC, the corresponding intercore communication patterns, 3-D on-chip thermal profile, as well as IR-drop distribution in the PDN can vary significantly. Based on this observation, we propose a novel design-time system-level application-specific cosynthesis framework that intelligently maps computation and communication resources on a die, for a given workload. The goal is to minimize the NoC power as well as chip-cooling power and optimize the 3-D PDN architecture; while meeting performance goals and satisfying thermal constraints, for a microfluidic cooling-based application-specific 3-D MPSoC. Our experimental results indicate that the proposed 3-D NoC-PDN cosynthesis framework is not only able to meet PDN design goals unlike prior 3-D NoC synthesis approaches, but also provides better overall optimality with the solution quality improvement of up to 35.4% over a probabilistic metaheuristic-based cooptimization approach proposed in prior work.

With the advances in semiconductor and circuit integrated technologies, the number of IP cores that can be integrated on one chip is becoming larger and larger. The traditional bus interconnection method of System on Chip (SoC) cannot meet the performance requirements of the Multi Processor System on Chip (MPSoC). Network on Chip (NoC) has improved the interconnect performance of IP cores. However, the conventional metallic interconnection constrains NoC to make greater improvement, while the mature of optical device integrated technology makes the trend of applying optical interconnection technology to chip promising. This paper proposes a cluster-based reconfigurable optical network on chip architecture (CRONoC), which uses a high bandwidth optical circuit switching network to transmit the inter-cluster data and an electrical packet switching network to control the optical network and transmit the intra-cluster data. By activating the resonators in the proposed inter-cluster crossbar structure, the topology is reconfigurable. Employing the proposed routing algorithm, the maximum distance of the network is reduced to 3 for the 64 core CRONoC. Finally, the performance of CRONoC in terms of end to end latency and network throughput under different traffic patterns is evaluated with OPNET. The simulation results show that the CRONoC architecture is suitable for the local and collective communications.

Multi-Processor Systems-on-Chips (MPSoCs) are a platform for a wide variety of applications and use-cases. The high on-chip connectivity, the programming flexibility, and the reuse of IPs, however, also introduce security concerns. Problems arise when applications with different trust and protection levels share resources of the MPSoC, such as processing units, cache memories and the Network-on-Chip (NoC) communication structure. If a program gets compromised, an adversary can observe the use of these resources and infer (potentially secret) information from other applications. In this work, we explore the cache-based attack by Bogdanov et al., which infers the cache activity of a target program through timing measurements and exploits collisions that occur when the same cache location is accessed for different program inputs. We implement this differential cache-collision attack on the MPSoC Glass and introduce an optimized variant of it, the Earthquake Attack, which leverages the NoC-based communication to increase attack efficiency. Our results show that Earthquake performs well under different cache line and MPSoC configurations, illustrating that cache-collision attacks are considerable threats on MPSoCs.

Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems, but also on high performance systems. In such systems, the data bandwidth requirements keeps increasing as the number of processing elements increases. Therefore, a Network-on-Chip (NoCs) communication architecture use to be preferred than a communication based on shared buses, because it provides higher communication performance. The probability of failure increases in this systems, due to these great advances in integration scales and the increasing number of components on chip. Therefore Fault Tolerance will become a key aspect on designing the near future VLSI SoC, and especially on their interconnection Network on Chip (NoC). This paper focuses on describe the particular aspects of NoCs, and the proposed fault-tolerant strategies for NoCs.

Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them partitioning, which organizes tasks considering their interaction before applying a mapping process. This paper introduces Partition Reduce (PR) — a task partitioning approach based on the MapReduce algorithm targeting homogeneous NoC based MPSoCs. We analyze the efficiency of PR for energy consumption (EC) minimization and load balance (LB). The results obtained from a set of experiments, with large number of tasks, demonstrate that PR is more effective on processing time and result quality when compared to the classic Simulated Annealing (SA). In addition, PR produces partitions with low energy consumption and rigorous load balance.

The performance of a multiprocessor system-on-chip (MPSoC) is not only dependent on the computational capabilities of on-chip processors but also depends on the communication medium connecting them. This has shifted the emphasis from computation to communication architectural design. In this paper, a dynamically reconfigurable network-on-chip (NoC) architecture has been proposed for reconfigurable MPSoC, as a solution to the increased communication needs, keeping low power, quality of service (QoS) and scalability of network in mind

Next generation multiprocessor systems-on-chip (MPSoCs) are expected to contain numerous processing elements, interconnected via on-chip networks, executing real-time applications. It is anticipated that runtime optimization algorithms which dynamically adjust system parameters with the purpose of optimizing the system's operation, will be embedded in the system software and/or hardware. In this paper, we present a methodology for simulating and evaluating system-level optimization algorithms, demonstrated by the case of on-chip dynamic task allocation applied to generic MPSoC architectures. Through this methodology, we are able to show that dynamic, system-level bidding-based task allocation can improve system performance, when compared to a round robin allocation, in popular MPSoC applications.