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Selective Hemispherical Grained Polysilicon Transformation for 256 MB, 1 GB Dynamic Random Access Memory and Beyond

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Abstract

Application of an ultrahigh vacuum vertical batch reactor for selective chemical vapor deposition of hemispherical grain (HSG) polysilicon on planar and three‐dimensional crown capacitor storage nodes is investigated. Comparison between selective HSG and other nonselective alternatives is drawn. An optimum pre‐HSG clean chemistry (with 60 Å overall oxide etch), suitable for 256 MB and I GB application, for both multi‐ and single tank wafer clean modules is recommended. This clean method maintains the integrity of the starting a‐Si (>5% of the original a‐Si thickness) prior to HSG transformation. Contamination issues related to the tool, preclean module, and the processing ambient are explored. Factors impacting within wafer and wafer‐to‐wafer reflectance and capacitance uniformity and the effect of particles and crystallization defects on HSG transformation are evaluated. Defect formation mechanisms and ways of minimizing defect density are also included. Effects of critical processing parameters on HSG grain characteristics in order to obtain maximum area enhancement factor and highest ratio for high density application (256 MB, 1 GB, and beyond) is explored in depth. Post‐HSG gas phase doping (800°C for 300 s) to achieve a ratio of >0.95 and its effect on surface roughness of HSG transformed a‐Si film is investigated. © 1999 The Electrochemical Society. All rights reserved.

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