Self adaptable multithreaded object detection on embedded multicore systems

Parallelizing software is a popular way of achieving high energy efficiency since parallel applications can be mapped on many cores and the clock frequency can be lowered. Perfect parallelism is, however, not often reached and different program phases usually contain different levels of parallelism due to data dependencies. Applications have currently no means of expressing the level of parallelism, and the power management is mostly done based on only the workload. In this work, we provide means of expressing QoS and levels of parallelism in applications for more tight integration with the power management to obtain optimal energy efficiency in multi-core systems. We utilize the dataflow framework PREESM to create and analyze program structures and expose the parallelism in the program phases to the power management. We use the derived parameters in a NLP (Non Linear Programming) solver to determine the minimum power for allocating resources to the applications.

Object detection is an important application for modern smart embedded devices. It enables the device to recognize the surrounding environment and perform intelligent applications. The intensive computation requirements make the object detection an expensive application running on the resource-constrained embedded device. Parallel processing on multi-core systems provides a platform to boost the performance. However, the memory bottleneck limits the performance scalability. Improving data locality of the on-chip cache has therefore become a critical design concern. This paper analyzed the memory behavior of a parallel Viola-Jones algorithm, and proposed a scheme to enhance the data locality of on-chip cache. By running a multi-threaded object detection algorithm on a cycle-accurate multi-core simulator, the proposed approach can achieve up to 58% better performance when compared with the original parallel program.

As the power density of modern electronic circuits increases dramatically, systems are prone to overheating. High temperatures not only raise packaging costs, degrade system performance, and increase leakage power consumption, but also reduce the system reliability. Due to many limits in single core design including the performance and the power density, the microprocessor industry has switched their attentions to multicore design to enable the scaling of performance. Thermal effects on multicore systems are still prominent issues. One typical thermal effect is the thermal-aware lifetime reliability, which has become a serious concern. In this paper, we address the issue on how to maximize the lifetime of multicore systems while maintaining a given aggregate processor speed. By applying sequential quadratic programming, we present how to derive the ideal speed for each core to maximize the system lifetime. We perform experiments on several multi-core platforms, which show that the proposed method can significantly outperform the existing approaches by minimizing the peak temperature of the system.

A multicomputer is a loosely coupled multiprocessor architecture, which is also called a cluster computer or just a cluster. It may be assembled from commercially available PCs and networking hardware as a low-cost alternative to rack mounted blades, interconnected through a high speed backplane, or to a high performance, tightly coupled, shared memory multiprocessor. Parallel software applications exploit parallelism in a cluster by distributing chunks of data among its remote nodes for simultaneous processing.Each remote node processes its chunk of data in parallel with the others and returns its partial result back to the master node for combination into a final result. When the chunk size, or system granularity, is just right, there is a balance between the network-transit time and the remote-processing time of the data; the distributed application runs at maximum efficiency and the system granularity is said to be optimal. That said, one wonders why there are no tools explicitly designed to help parallel software designers and performance analysts determine the optimal granularity size of a given cluster!We present a back-to-basics approach, application-level program named McGAT, for Multi-computer Granularity Assessment Tool. The user specifies a range of chunk sizes to analyze, along with a remote node's processing time estimate for a particular sized chunk. McGAT is not a simulation, but a parallel application that runs on the user's hardware, distributing chunks of data to each of the cluster's remote nodes. Each node responds after an amount of time necessary to process that data, based on the user's processing time estimates. McGAT reports system throughput for each chunk size over the user-specified range.The chunk size with the maximum throughput indicates the optimal granularity of the system on which it is run, which is a key parallel software design component. The user may then choose a chunk size that provides maximum throughput within the requirements of his or her specific application.Our presentation includes graphs comparing the results from runs on a 3-, 4-, and 5-node Linux-based PC cluster, interconnected through both 10 and 100 Mbps Ethernet. We plan to expand our knowledge base to include larger numbers of nodes, and a virtual ring to complement or virtual star communications protocol.McGAT may be used to establish a performance baseline, and again later to quantify the effect of any subsequent changes to the cluster. McGAT is offered as open source software, and a beta release for Linux based platforms is available for download from the DSRLab website under the GNU General Public License.

In-memory computing (IMC) has been proposed to overcome the von Neumann bottleneck in data-intensive applications. However, existing IMC solutions could not achieve both high parallelism and high flexibility, which limits their application in more general scenarios: As a highly parallel IMC design, the functionality of a MAC crossbar is limited to the matrix-vector multiplication; Another IMC method of logic-in-memory (LiM) is more flexible in supporting different logic functions, but has low parallelism. To improve the LiM parallelism, we are inspired by investigating how the single-instruction, multiple-data (SIMD) instruction set in conventional CPU could potentially help to expand the number of LiM operands in one cycle. The biggest challenge is the inefficiency in handling non-continuous data in parallel due to the SIMD limitation of (i) continuous address, (ii) limited cache bandwidth, and (iii) large full-resolution parallel computing overheads. This article presents GRAPHIC, the first reported in-memory SIMD architecture that solves the parallelism and irregular data access challenges in applying SIMD to LiM. GRAPHIC exploits content-addressable memory (CAM) and row-wise-accessible SRAM. By providing the in-situ, full-parallelism, and low-overhead operations of address search, cache read-compute-and-update, GRAPHIC accomplishes high-efficiency gather and aggregation with high parallelism, high energy efficiency, low latency, and low area overheads. Experiments in both continuous data access and irregular data pattern applications show an average speedup of 5x over iso-area AVX-like LiM, and 3-5x over the emerging CAM-based accelerators of CAPE and GaaS-X in advanced techniques.

This thesis presents techniques for modeling and control of X-ray image processing tasks, aiming at the fluent execution of a multitude of diagnostic and interventional X-ray imaging applications on a multi-core computing platform. A general trend in medical imaging systems is the execution of image processing on general-purpose programmable platforms, instead of specific dedicated hardware solutions. This even holds for the newest functionality such as image analysis, which performs computations in a more stochastic manner, rather than stream-based processing. The trend of more dynamic image processing and the new analysis functions in X-ray imaging, combined with the desire for more programmable and flexible future systems forms the starting point of our research. The first contribution of this thesis is the modeling and optimization of the processing performance of stream-based medical imaging tasks, in particular image quality enhancement for interventional X-ray. We have defined rules for specifying and dividing image processing tasks for parallel processing, to optimize the related memory communication. Similarly, for the computing architecture, we have specified the detailed timing requirements for data storage and communication, incorporating memory-access times. In the initial situation, the computing system was fully loaded, both in terms of memory and computation, and the latency was strongly time varying and could not be predicted. Our modeling has yielded a good understanding of the actual execution and its critical factors. The model has eventually lead to an approach for task splitting leading to a sharper system optimization with respect to essential parameters, such as latency. However, the method for building the model is time consuming. The same holds for the architecture. Nevertheless, the experiment has been highly valuable since the system optimization is associated with a considerable system cost and the resulting alternative execution architectures have provided ways for cost reduction or adding attractive functionality to the same system, which currently is executed on an additional separate platform. The second contribution of this thesis is the modeling and prediction of the computation time of feature-based medical imaging tasks, where the task complexity is non-deterministic and the resource demands fluctuate with the image content. We have focused in particular on applications for advanced diagnosis with image analysis and motion-compensated subtraction imaging. We demonstrated that the computation time for tasks with purely random resource usage can be successfully predicted with zero-order Markov chains. Furthermore, first-order Markov chains are used if temporal correlation between the computation time statistics exists for only short periods of time. For structural correlations between image frames, scenario-based methods have to be added to the obtained prediction model, extracted from the flow graph of tasks. Alternatively, when the computational complexity depends on external (spatial) factors, the prediction model is based on spatial (look-ahead) prediction. Experimental results have shown that it is possible to predict the computation time of feature-based medical image applications, even if the flow graph dynamically switches between groups of tasks. We have found an average accuracy for two different application scenarios between 95 – 97%, with sporadic excursions of the prediction error up to 20 – 30%. The third contribution of this thesis is the design of a control system for the fluent execution of a set of applications on a multi-core platform, where some of the applications have a fluctuating resource demand and others have strict low-latency requirements. As a possible solution, we have implemented options for scalability in applications for three application scenarios, using task scaling, task skipping and task delaying. A Quality-of-Service (QoS) control system then maintains constant throughput and latency by dynamically switching between application quality modes. A global resource manager maintains the overall resource usage of the system and local application controllers are responsible for resource estimation and quality control of each individual application. The global resource manager is based on a modified version of the Lagrangian relaxation algorithm that searches for suitable combinations of quality levels for a set of concurrent running applications. The research has been validated by executing three medical imaging applications in parallel, from which two are critical in latency. It is interesting to know that the above solution has a high industrial relevance because it can facilitate in reducing system costs for applications that are already released on the market. The work has resulted in a solution featuring a combination of both interventional and diagnostic signal processing, which are executed on a single computing device with nearly the same quality, as compared to two separated computers with those tasks in the original setting. Furthermore, the techniques can be employed for different classes of systems, with different cost-performance points.

With exponentially increased transistor density on multi-core platforms, the power explosion and consequently soaring chip temperature have become critical challenges for system designers. Moreover, the increasing chip temperature results in higher leakage power, hence further aggravates the increment of the overall power consumption [1]. Thus, the dramatically growing power/energy consumption and chip temperature severely affect the cost, reliability and performance of the systems [4].

GALS-Designer is a framework for the design of software systems which comply with the formal Globally Asynchronous Locally Synchronous model of computation (GALS). Those systems consist of single or multiple GALS programs and their immediate environment, which can be other programs and any other modules described in SystemC. The framework integrates our libGALS library for writing GALS programs and SystemC. It enables modeling and simulation of single and multiple GALS programs within the single SystemC executable model on the host (simulation) operating system. The same GALS programs can then be run without SystemC on a target operating system for which the libGALS runtime library is available. The use of the GALS-Designer is demonstrated on an example of a complex embedded system. As libGALS can execute on multiprocessor platforms both the simulation and target models of the GALS system can take advantage of multiprocessor and multicore systems, which is not possible when using standard SystemC. Results of running simulation models of GALS programs demonstrate simulation performance improvement when executing on multicore platforms.

In multi-core systems, main memory is a major shared resource among processor cores. A task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared main memory system. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to reduce this interference and provide an upper bound on the worst-case interference on a multi-core platform that uses a commercial-off-the-shelf (COTS) DRAM system. We explicitly model the major resources in the DRAM system, including banks, buses, and the memory controller. By considering their timing characteristics, we analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel. We find that memory interference can be significantly reduced by (i) partitioning DRAM banks, and (ii) co-locating memory-intensive tasks on the same processing core. Based on these observations, we develop a memory interference-aware task allocation algorithm for reducing memory interference. We evaluate our approach on a COTS-based multi-core platform running Linux/RK. Experimental results show that the predictions made by our approach are close to the measured worst-case interference under workloads with both high and low memory contention. In addition, our memory interference-aware task allocation algorithm provides a significant improvement in task schedulability over previous work, with as much as 96 % more tasksets being schedulable.

Dedicated clusters are becoming commonly used for high performance parallel processing. Computers of a non-dedicated cluster are often idle or lightly loaded. These under utilised computers can be employed to execute parallel applications. Thus, they have to be shared by parallel and sequential applications, which could lead to the improvement of their execution performance. There is a lack of experimental study showing the behaviour and performance of executing parallel and sequential applications concurrently on a non-dedicated cluster. We present the result of an experimental study into load balancing of a mixture of parallel and sequential applications on a non-dedicated cluster.

MOSART project addresses two main challenges of prevailing architectures: (1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; (2) The difficulties in programming heterogeneous, multi-core platforms MOSART aims to overcome these through a multi-core architecture with distributed memory organization, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: (1) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.KeywordsAbstract Data TypeWorkload ModelPower Management SystemMemory AllocatorJPEG EncoderThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The distributed file system, HDFS, is widely deployed as the bedrock for many parallel big data analysis. However, when running multiple parallel applications over the shared file system, the data requests from different processes/executors will unfortunately be served in a surprisingly imbalanced fashion on the distributed storage servers. These imbalanced access patterns among storage nodes are caused because a). unlike conventional parallel file system using striping policies to evenly distribute data among storage nodes, data-intensive file system such as HDFS store each data unit, referred to as chunk file, with several copies based on a relative random policy, which can result in an uneven data distribution among storage nodes; b). based on the data retrieval policy in HDFS, the more data a storage node contains, the higher probability the storage node could be selected to serve the data. Therefore, on the nodes serving multiple chunk files, the data requests from different processes/executors will compete for shared resources such as hard disk head and networkbandwidth, resulting in a degraded I/O performance. In this paper, we first conduct a complete analysis on how remote and imbalanced read/write patterns occur and how they are affected by the size of the cluster. We then propose novel methods, referred to as Opass, to optimize parallel data reads, as well as to reduce the imbalance of parallel writes on distributed file systems. Our proposed methods can benefit parallel data-intensive analysis with various parallel data access strategies. Opass adopts new matching-based algorithms to match processes to data so as to compute the maximum degree of data locality and balanced data access. Furthermore, to reduce the imbalance of parallel writes, Opass employs a heatmap for monitoring the I/O statuses of storage nodes and performs HM-LRU policy to select a local optimal storage node for serving write requests. Experiments are conducted on PRObE's Marmot 128-node cluster testbed and the results from both benchmark and well-known parallel applications show the performance benefits and scalability of Opass.

The skyline query is an efficient data analysis tool for multi-criteria decision making that has received significant attention in the database community. As multi-core architectures have gone mainstream, we present a new parallel skyline query algorithm that can be applied to multi-core and multiprocessor systems, to progressively return skyline points as they are identified efficiently. In this paper, we proposed a parallel skyline algorithm which can eliminate redundant computations and improve parallelism of the skyline query. Experimental results show that our algorithm successfully exploits the features of multiple cores to improve the performance of skyline computation for large high-dimensional datasets.

The current development of high performance parallel supercomputing infrastructures are pushing the boundaries of applications of science and are bringing new paradigms into engineering practices and simulations. Earthquake engineering is also one of the major fields, which benefits from above by looking for solutions in grid computing and cloud computing techniques. Generally, earthquake simulations involve analysis of petabytes of data. Analyzing these large amounts of data in parallel in thousands of nodes in computer clusters results in gaining high performances. Open source cloud solutions such as Hadoop MapReduce, which is highly scalable and capable of processing large amount of data rapidly in parallel on large clusters provide better solution compared to RDBDM. Both GPUs and MapReduce are designed to support vast data parallelism. For performance considerations, GPU computing could be adopted over low performing CPU systems. This paper discusses MapReduce system using Hadoop and Mars. Mars is a MapReduce framework on graphics processor. Hence, the proposition is to use GPU based systems for earthquake simulations in which Digital elevation model 3D data sets are fully materialized where scientist can make use of these data for various analysis and simulations.

The popularity of multi-core systems makes software parallelization become an important way to improve performance. As a mainstream XML query language, XQuery is the core of XML processing. It is critical to take full advantage of multi-core computing to improve XML processing performance through parallelization of XQuery. However, usually it is difficult to parallelize XQuery programs because of the nested style of XQuery expressions. Moreover, implicit parallelism is necessary to simplify the development of parallel XML application. In this paper, we propose an automatic parallelization approach, which can automatically select proper types of parallelism for a specific XQuery query. Specifically, we propose a functional intermediate language called pFXQL (parallel Functional XML Query Language) to describe parallel query plans. pFXQL has parallel semantics and is well complied with XQuery. We propose a cost model to effectively support plan generation and the selection of a preferred plan. The model estimates both computational cost and parallel cost. We implement our approach in XQuery engine and conduct experiments on various multi-core systems. Experimental results verify the effectiveness of our approach.