Self-timed Reinforcement Learning using Tsetlin Machine

We present a procedure for synthesizing initializable asynchronous circuits from functionally uninitializable Signal Transition Graphs (STG). After characterizing the necessary conditions for functional uninitializability, we propose a technique that transforms the original STG into an equivalent, functionally initializable STG. It is shown that initializability can be achieved by sacrificing minimal concurrency without violating the syntactic properties of the STG required for a hazard-free implementation. The synthesis of a trigger module illustrates this procedure. >

Asynchronous circuits are a promising type of digital circuit that still see moderate usage in today’s commercial products, which has often been linked to the adaptation challenges that are posed within industry, e.g. time required to develop new tools and train designers versus using existing synchronous tools to quickly meet market demands. Several formal models were introduced to aid with the design of asynchronous circuits, including Burst-Mode (BM) Specifications and Signal Transition Graphs (STGs). BM specifications resemble synchronous Finite State Machines (FSMs) allowing circuit designers to easily adapt and use them, however their circuit implementations may be limited due to declining tool support. STGs have access to well-established tools that produce optimal hazard-free circuit implementations, but they are seen as too different by the industry. In this paper, we present a new ‘co-design’ methodology that bridges the gap between BM specifications and STGs by using a formal model called Burst Automaton (BA). BA is a generic FSM-like model that acts as a framework for enabling interoperability between many different formal models, and offers several benefits that BM specifications and STGs can leverage. Our ‘co-design’ methodology is implemented in Workcraft, and is evaluated on several benchmarks showing an improved synthesis flow.

A signal transition graph (STG) embodies the causal relationships among signal transitions in a system, and provides a useful starting point for the synthesis of asynchronous circuits. The prevalent synthesis techniques require the input STG to possess the unique state coding (USC) property. This paper describes an algorithm to ascertain whether a given STG has the USC property. The algorithm is path-oriented, and has the advantage of operating directly on the STG rather than a state graph. This approach has the advantage of being easier to visually and intuitively correlate with the STG specification, and therefore suggest ways in which a designer (or tool) may modify the input STG if it does not satisfy the USC property. The technique can also be used to compute the input set of a signal. >

Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. The refinement process is generally done automatically using heuristics. It often produces suboptimal solutions or sometimes fails to solve the problem. Thus manual intervention by the designer may be required. A framework is presented for an interactive refinement process aimed to help the designer. It is based on the visualisation of conflict cores, i.e. sets of transitions causing encoding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.

A new asynchronous wrapper circuit is proposed based on standard cells for the realization of point to point high speed seamless data transmission. The wrapper is realized from the Signal Transition Graph (STG) by Petrify based on the fundamental GALS system structure. The asynchronous circuit includes the design of synchronous/asynchronous interface and local clock which can be suspended. The traditional EDA tools are merged together with asynchronous circuit design, and the wrapper only has standard cells but not special asynchronous logic gates. The simulation and verification were made by Modelsim and Quartus respectively, and the results have shown that the GALS system works properly and has a preferable performance.

Verifying the correctness of asynchronous sequential circuits is one of the most important tasks in asynchronous design. However, the absence of the global clock and the variation of gate delays in asynchronous circuits make the verification a formidable task. In this paper, a method that can perform efficient timing analysis of gate-level implementation of asynchronous circuits is presented. The method is based on specific behavior given by the Signal Transition Graph (STG). By modifying the STG into the STG control graph, the circuit can be simulated correctly with automatic test generation. The ternary logic is introduced in order to describe the behaviors of gates with bounded inertial delays. The program is written in VHDL. Lastly in this paper, one of the many simulation results to detect hazards is presented.

Signal Transition Graphs (STGs) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STGs some method based on Occurrence nets (OCN) and its prefix, called unfolding, has been proposed. OCNs can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating substate space of a given STG using the structural properties of OCN. The proposed method can be seen as a parallel algorithm for deriving a logic function.

We propose a novel method to eliminate dynamic hazards in asynchronous circuits synthesized from the signal transition graph (STG) specifications. We first review a relationship between syntactic constraints such as liveness and complete state coding at the STG level and the hazard properties at the gate level. Using this relationship, we identify the cause of dynamic hazards and remove them by an iterative factoring method. Each factoring entails augmenting the given STG with an internal signal. This method is applicable to both combinational and sequential circuits, and results in hazard-free multi-level implementations from STG specifications.

A method is presented for deriving a system of parallel extended-burst-mode (XBM) machines from a signal transition graph (STG) specifying required input-output behaviour. First, a primitive finite-state machine is derived as the most general, sequential solution, from which allowable concurrency can still be recognized. Output concurrency is dealt with by decomposition (output partitioning, omission of irrelevant inputs). The component FSMs, with input concurrency only, are tested for XBM feasibility and-if positive-their XBM specifications are constructed. The entire procedure is systematic and is illustrated by deriving two XBM machines from an STG with input and output concurrency. We propose to view the STG as the most general and most precise causal specification of any asynchronous design problem, above and beyond considerations of circuit models and delay assumptions.

This paper presents a novel design method for asynchronous control logic targeting successive approximation register (SAR) analog-to-digital converters (ADCs). This work is based on modeling the control logic for SAR ADCs using signal transition graphs (STGs). Different from conventional synchronous controllers, the proposed method results in asynchronous controllers driven by the causality of signals rather than relying on clocks to control the conversion process. Moreover, the proposed asynchronous control logic can be modularized through the handshake protocol, making it possible to build ADCs of arbitrary precision based on single-bit control units. This work results in a formal, model-based asynchronous design flow for SAR ADC control, which is shown to produce resulting circuits of similar speeds but great power efficiency improvements.

We propose a design flow for asynchronous circuits that closely mimics the standard synchronous ASIC design flow. Key elements of the flow are HDL-based specification, logic synthesis and physical design. In this work we present a proposal for using a standard HDL, Verilog, to specify an asynchronous control circuit at the behavioral level. This pecification is automatically translated in a Signal Transition Graph, that can then be automatically synthesized by existing tools.

A constraint satisfaction framework is proposed that can guarantee necessary and sufficient conditions for a state graph assignment to result in a transformed state graph that is race-free. Performing transformations at the state graph level has the advantage that the requirements imposed on the initial signal transition graph (STG) are very weak. Unlike previous methods, the initial STG need not be a live, safe, free choice net. The only requirement is that the corresponding initial state graph should be finite and connected, and have a consistent state assignment. Hence, a very broad range of STGs can be synthesized. The transformation achievable using the proposed framework correspond to very complex transformations on STGs. Even transformations that convert a free choice net into a correct non-free choice net, and a 1-safe net into a correct 2-safe net are feasible. Addition of transitions that do not follow the Petri net firing rule is also possible. >

Switched Capacitor DC-DC converters play an important role in low power technologies such as energy harvesting systems as they can provide step-up voltage outputs with lower inputs. This paper models and analyses Switched Capacitor DC-DC converters with Signal Transition Graphs, which are originally used for modelling asynchronous circuits. With this new approach, the causality relations between phases, capacitors and internal signals in Switched-Capacitor DC-DC converter can be described distinctly, especially for some complicated converters. This is the first attempt at generating formal models for these types of components, which previously have been described by natural language and waveforms.

The synthesis of asynchronous circuits is difficult in VLSI design. Transition based specification such as signal transition graphs (STGs) are simple and powerful in specifying and synthesizing asynchronous behavior. A relationship is established between the signal transition graph syntactic constraints, i.e., persistency and complete state coding (CSC). A direct proof is presented which shows that a persistency violation either does not affect hazards or, if it does, there results a complete state coding violation. The authors' results give the conditions under which a persistency violation may lead to a complete state coding violation. >

Asynchronous circuits have potential advantages of higher speed and lower power consumption compared to their synchronous counterparts, but their poor CAD support is a major issue limiting adoption. In this paper, we present an integrated timing and power analysis engine capable of handling large asynchronous circuits. For timing, we introduce the notion of performance and correctness slack for asynchronous circuits; for power, we compute both the static and dynamic components. We provide a hierarchical approach to constructing the event-dependency graph, and use the Galois framework for parallelization to achieve fast runtime. The net result is Cyclone, a fast and accurate engine for both static timing and power analysis of asynchronous circuits.