Sensitivity and Detection Problems

Recently, digital Intermediate Frequency (IF) waveform generators and receivers are introduced in modern radar systems to reduce the cost, size, and achieve better performance. Moreover, digital IF waveform generators achieve the requirements of high resolution and complex modulation schemes. Digital receivers have better sensitivity, wider dynamic range and lower noise Figure than analog receivers. Digital IF waveform generators and receivers work well in conjunction with a high-speed Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC). In this paper, the design and implementation of high-speed data acquisition circuits (ADC and DAC) to generate and acquire IF waveforms are presented. Different modulated waveforms are generated digitally using Field Programmable Gate Array (FPGA). The corresponding digital receiver, including digital phase detection and matched filtering, is designed and implemented on the same FPGA chip. Design and implementation of a Printed Circuit Board (PCB) including FPGA chip and its required circuitry are introduced. The proposed design is simulated using Computer-Aided Design (CAD) tools and verified experimentally through laboratory testing.

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

Digital pulsed ultra wideband (UWB) receivers offer numerous advantages compared to architectures based on analogue correlation, but present unique implementation challenges. The specification of the Analogue-to-Digital Converter (ADC) resolution constitutes one of the most critical activities in the design of digital UWB receivers. Moreover, multi-bit ADCs must be associated with an Automatic Gain Control block which avoids the sub-optimal regimes of the ADC dominated by quantisation or saturation noise. This paper shows how to determine the ADC resolution requirements and the optimal Automatic Gain Control (AGC) settings for the general class of digital receivers. We conclude that 3 bits provide sufficient resolution on condition that the AGC scales the input signal at a reference root mean squared (RMS) level of half the ADC saturation voltage.

Several integrated capacitors can be used in analog-to-digital converters (ADCs) for complementary-metal-oxide-semiconductor (CMOS) image sensors, including metal-insulator-metal (MIM), metal-oxide-metal (MOM) and metal-oxide-semiconductor (MOS) capacitors. Among those capacitors, MOS capacitors have the highest capacitance density per unit area but a large voltage dependency, which will cause the non-linearity of ADCs. Recently, several types of ADCs are employed for column-parallel ADCs, including a single-slope (SS), sigma-delta (ΔΣ), successive approximation (SAR) ADC, cyclic ADC and folding-integration/cyclic (FI-Cyclic) ADCs. A Cyclic ADC is well known for its ability to achieve medium resolution while requiring a small silicon area and implementing a reasonable conversion rate of one conversion cycle per bit of resolution. Compared with other ADCs, the cyclic ADC has superiority in overcoming the difficulty of compatibility between ADC speed and bit resolution, while maintaining low-noise and HDR. On the basis of inheriting the advantage of cyclic ADC, FI-Cyclic ADC has better performance on low noise, high grayscale resolution and resulting high dynamic range.

There is proposed method of integral nonlinearity identification of conversion characteristic of analog to digital converters (ADC) in this paper, which is based on error compensation of voltage divider after conversion results processing. Also there is presented some results of investigation of sigma-delta ADC by proposed method.

Analog-to-digital conversion allows physical signals to be processed using digital hardware. This conversion consists of two stages: Sampling, which maps a continuous-time signal into discrete-time, and quantization, i.e., representing the continuous-amplitude quantities using a finite number of bits. This conversion is typically carried out using generic uniform mappings that are ignorant of the task for which the signal is acquired, and can be costly when operating in high rates and fine resolutions. In this work we design task-oriented analog-to-digital converters (ADCs) which operate in a data-driven manner, namely they learn how to map an analog signal into a sampled digital representation such that the system task can be efficiently carried out. We propose a model for sampling and quantization which both faithfully represents these operations while allowing the system to learn non-uniform mappings from training data. We focus on the task of symbol detection in multipleinput multiple-output (MIMO) digital receivers, where multiple analog signals are simultaneously acquired in order to recover a set of discrete information symbols. Our numerical results demonstrate that the proposed approach achieves performance which is comparable to operating without quantization constraints, while achieving more accurate digital representation compared to utilizing conventional uniform ADCs.

In this work, we present the computation of minimum noise required at the input of Analog to Digital Converter (ADC) in radar receiver to maintain the required statistics of noise in radar system. The work puts forward the analysis which computes the minimum noise required at the input of the ADC in radar receiver so that the noise introduced by the ADC is comparably negligible so as to maintain the required noise statistics in the receiver. This further ensures that the associated loss is minimal. The work quantitatively presents the gain reduction that can be achieved in the frontend of the receiver as we go for ADCs with higher number of bits. The paper presents detailed analysis of multiple test cases considering ADCs of different bits, the associated loss in Signal to Noise Ratio (SNR) computation and receiver gain variation as compared to a reference ADC.

Dithering improves the linearity of A/D converters (ADCs). Wagdy and Goff (1994) have developed a criterion for assessing the deviation of ADC transfer characteristics from the unity-gain line. This criterion is based on a closed-form formula for the deviation factor D derived from the characteristic function of the ADC quantization error function. This approach was extended further by Wagdy (1996) to include nonideal ADCs. The results in that work pertain to additive dither, but a closed-form formula for subtractive dither may be very difficult to derive. In this paper, the ADC is modeled and dither is simulated using a software random number generator. First, additive dithering with continuous (analog) uniform (rectangular) probability density function (RPDF) is considered. The cases of an ADC with no errors, single-bit error, or multi-bit errors are investigated. Results are in excellent agreement with the previous ones, which validates the formulae therein. Second, the author presents new results using discrete (digital) rectangular dither (DRPDF). This dither type is generated via a D/A converter (DAC) whose number of bits, k, is greater by del than the ADC number of bits, m. For various values of del, subtractively-dithered ADCs outperform additively-dithered ones as far as D is concerned. Also, the effect of increasing del on D for an ADC is investigated for the subtractive dither case, thus providing some quantitative results which are useful for the designer.

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

The readout of silicon strip sensors in the upgraded Tracker System of Large Hadron Collider beauty (LHCb) experiment will require a novel complex Application Specific Integrated Circuit (ASIC). The ASIC will extract and digitise analogue signal from the sensor and subsequently will perform digital processing and serial data transmission.One of the key processing blocks, placed in each channel, will be an Analogue to Digital Converter (ADC). A prototype of fast, low-power 6-bit Successive Approximation Register (SAR) ADC was designed, fabricated and tested. The measurements of ADC prototypes confirmed simulation results showing excellent overall performance. In particular, very good resolution with Effective Number Of Bits (ENOB) 5.85 was obtained together with very low power consumption of 0.35 mW at 40 MS/s sampling rate. The results of the performed static and dynamic measurements confirm excellent ADC operation for higher sampling rates up to 80 MS/s.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

This paper presents a parallel architecture for a photonic Analog to Digital Converter (ADC) in a direct conversion receiver. A novel technique for the generation of time and wavelength interleaved laser source having a broad spectrum and a repetition rate of 8 GHz is proposed for the sampling of the photonic ADC. The quantization is realized in electrical domain by employing four state of the art ADCs , each having a sampling rate of 2 GHz and a resolution of 10 bit. We investigate the performance of our novel architecture by computing the Signal to Noise Ratio and comparing it with the conventional electronic ADC. Additionally we have also observed the effect of laser jitter on the sensitivity of a direct conversion receiver.

In this work, first real hardware implementation results of CDR (Compressive Digital Receiver) are detailed. CDR is a digital receiver technology, which estimates frequency, amplitude, pulse-width etc. parameters of the incoming signal without ambiguity in frequency, by sampling the signal at rates far below the Nyquist limit based on compressive sensing theory. It is observed that the implemented hardware structure can resolve an instantaneous bandwidth of 2 GHz by using only two ADCs (Analog to Digital Converter) running at 200 MHz sampling frequency. It is argued that the CR system can be used as a digital receiver especially for Electronic Support Systems since it can monitor a wide spectrum by sampling at a very low rate.

This paper presents the design of a low-power high-dynamic-range analog-to-digital converter (ADC) for solid-state radiation detectors, in particular Cadmium Zinc Telluride (CZT). The core of the ADC consists of a Wilkinson-type digitizer, a digital control unit and a 9-bit counter. The analog core of the ADC operates from a 3.3 V supply while the supply for the digital control circuitry is 1.2 V. The input dynamic range of the ADC is 2.7 V and the ADC consumes 631 μW. The ADC is designed and laid-out in a standard 0.13-μm CMOS process and occupies 0.026 mm2. Post-layout simulation results show that the signal-to-noise and distortion ratio (SNDR) of the ADC is just over 50 dB which corresponds to an effective number of bits (ENOB) of approximately 8. The simulated differential and integral nonlinearities (DNL and INL) are ±0.065 LSB and 0.954 LSB, respectively.

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.