SENTRY: Protecting System-on-Chip Designs against Supply-Chain Attacks

The size of the program code has become a critical design constraint in embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Furthermore, large memories may increase the power consumption due to higher memory I/O bandwidth. Program compression methods have been proposed to improve the code density and hence minimize the area and power consumption of the program memory. Dictionary-based compression is one of the most often used compression methods due to its simplicity. The drawback of the dictionary-based compression is the limited programmability after compression when the dictionary is implemented using ROM or standard cells. In this paper, a method based on extending the dictionary is proposed for a customizable processor architecture with parallel resources to maintain the programmability also after the compression has been made. The obtained results indicate that with the proposed approach, the programmability can be maintained with a small overhead in area and power consumption.

Multiantenna systems and more particularly those operating on multiple input and multiple output (MIMO) channels are currently a must to improve wireless links spectrum efficiency and/or robustness. There exists a fundamental tradeoff between potential spectrum efficiency and robustness increase. However, multiantenna techniques also come with an overhead in silicon implementation area and power consumption due, at least, to the duplication of part of the transmitter and receiver radio front-ends. Although the area overhead may be acceptable in view of the performance improvement, low power consumption must be preserved for integration in nomadic devices. In this case, it is the tradeoff between performance (e.g., the net throughput on top of the medium access control layer) and average power consumption that really matters. It has been shown that adaptive schemes were mandatory to avoid that multiantenna techniques hamper this system tradeoff. In this paper, we derive smartMIMO: an adaptive multiantenna approach which, next to simply adapting the modulation and code rate as traditionally considered, decides packet-per-packet, depending on the MIMO channel state, to use either space-division multiplexing (increasing spectrum efficiency), space-time coding (increasing robustness), or to stick to single-antenna transmission. Contrarily to many of such adaptive schemes, the focus is set on using multiantenna transmission to improve the link energy efficiency in real operation conditions. Based on a model calibrated on an existing reconfigurable multiantenna transceiver setup, the link energy efficiency with the proposed scheme is shown to be improved by up to 30% when compared to nonadaptive schemes. The average throughput is, on the other hand, improved by up to 50% when compared to single-antenna transmission.

Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One of typical DPGA architectures is a multi-context one. Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained reconfigurable architecture called reconfigurable context memory (RCM) is presented based on the fact that there are redundancy and regularity in configuration bits between different contexts. A floating-MOS functional pass-gate, where storage and switch functions are merged, is used to construct the RCM area-efficiently.

Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate (FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The transistor count of the proposed multi-context switch (MC-switch) is reduced to 10% in comparison with SRAM-based one. The transistor count of the proposed MC-switch is also reduced to 20% in comparison with the MC-switch that uses floating-gate MOS transistors just as storage device. The test chip is designed using a 0.35mum EPROM technology, and the area of the proposed MC-FPGA is reduced to about 50% of that of a conventional MC-FPGA

Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one.

Speculative adders divide addition into subgroups and execute them in parallel for higher execution speed and energy efficiency, but at the risk of generating incorrect results. In this paper, we propose a lightweight correlation-aware speculative addition (CASA) method, which exploits the correlation between input data and carry-in values observed in real-life benchmarks to improve the accuracy of speculative adders. Experimental results show that applying the CASA method leads to a significant reduction in error rate with only marginal overhead in timing, area, and power consumption.

Due to the downscaling of transistor feature sizes, nowadays integrated circuits are more vulnerable to various effects that can cause faults during operation. Appropriate mechanisms for handling these faults in the field are required to meet certain dependability demands nonetheless. At the same time, the overhead in chip area and power consumption that is caused by such fault tolerance techniques needs to be reasonable. This calls for a dependability aware design space exploration which carefully evaluates the costs and benefits of various fault tolerant implementations of the system. This paper first introduces a tool that supports this design space exploration for hardware redundancy based fault tolerance. Among other features, it offers very fast overhead estimations for the supported set of fault tolerance techniques. The paper describes in detail how the estimations of the power overhead are performed. The accuracy of these estimations is evaluated by comparison with power analysis results obtained by a commercial EDA tool.

The distribution of traffic in the WiNoC system is variable in time and space. Based on this feature, researchers have proposed a kind of scheme which is dynamic MAC mechanism to adaptively allocate bandwidth and improve data communication efficiency. However, this kind of scheme has a large power consumption overhead. Therefore, this paper designs a dynamic and finegrained method based on different wireless usage rates. The fine-grained distributed power gate control scheme dynamically switches the power gated working state according to different mechanisms of the MAC mechanism, and effectively reduces the data communication power consumption in the network with a small area overhead. Experiments show that: although this scheme increases the area overhead by 6.42%, it reduces the power consumption overhead by 26.4%

Due to the high integration required for system application, the three-dimensional chip may resolve this requirement. The three-dimensional vertically stacking (3D-stacking) systems have been proposed to satisfy these requirements. However, the 3D-stacking system contains several design risks from its long layer interconnections. For a 3D-stacking system, it is difficult to identify where the numerous power and signal-interconnection are open-, shorted-fault, or resistive-short has accrued. Therefore, solving these interconnection problems is necessary. A feasible interconnection quality-evaluation, fault-diagnosis, and connection-reconfigurable mechanism are proposed. The proposed interconnection-measurement-recovery (IMR) mechanism will make it easy to find interconnection faults and make recovery in 3D-Stacking systems. The proposed IMR can detect interconnection open, short, bridge and resistive defects with the path-reroute mechanism. Future more, the signal transmission quality can be measured. This measurement provides to monitor signal propagation in pico-second accuracy. IMR has less extra area and power consumption overhead. The feasibilities of the proposed mechanism have been justified by 2D-chip and 3D-stacking MorPack both systems.

No-fault-founds (NFFs) threaten the dependability of highly dependable systems in avionic and car industries. Moreover, they drastically increase the test and maintenance costs. One of the main causes of NFFs is intermittent resistive faults (IRFs). IRFs mostly occur due to unstable and marginal interconnections. This paper proposes a new periodic testing method to detect IRFs in interconnections at the chip and the board level. The proposed method is based on on-chip embedded test instruments (ETIs), which are scalable, fully digital, and With a low hardware cost. As a case study, a network-on-chip (NoC) infrastructure with a mesh topology has been utilised. The implementation of the testing method requires a small chip area and power consumption overheads being 3% and 2.5%, respectively. In this paper, first, IRF detection at the chip level has been investigated using simulation-based fault injections in selected interconnections of the NoC. Then, the effectiveness of the proposed method at the board level has been verified by hardware-based fault injections as well as thermal cycling experiments on actual solder joints. The experimental results demonstrated that the on-chip ETIs can be reused effectively to detect IRFs at the board level.

This paper proposes three methods to mitigate and tolerate SEU-caused errors on the configuration bits of SRAM-based field programmable gate arrays. The proposed methods are based on error detection and correction codes which are able to detect or correct SEU-caused errors in Switch Modules. The effects of proposed methods on the various parameters such as area, delay and power consumption for ten ITC'99 benchmark circuits have been evaluated with synopsis® CAD tool and compared with previous work. The experimental results show that the proposed methods can detect or correct 100% single errors in Switch Modules by imposing area overhead between 2% and 60%, delay overhead between 25% and 100% and power consumption overhead between 1% and 25%.

Since the Internet of Things (IoT) will be entwined with everything we use in our daily life, the consequence of security flaws escalates. Smart objects will govern most of the home appliances and car engines yielding potential disaster scenarios. In this context, successful attacks could lead to chaos and scary scenarios (www.darkreading.com). Unprotected personal information may expose sensitive and embarrassing data to the public and attacks may threaten not only our computers and smart devices, but our intimacy and perhaps our lives too. Because persons and objects will be bonded with each other, user consent becomes critical. Therefore, thing, object, and user Identity will be the focus of future IoT security solutions, yielding a Trust, Security, and Privacy (TSP) paradigm, which may constitute the Achilles' heel of IoT. While security issues are quite straightforward, mainly from background knowledge, privacy issues are far more complex. Privacy constitutes a rather challenging task, even for the m...

System security is an increasingly important design criterion for many embedded systems. These systems are often portable and more easily attacked than traditional desktop and server computing systems. Key requirements for system security include defenses against physical attacks and lightweight support in terms of area and power consumption. Our new approach to embedded system security focuses on the protection of application loading and secure application execution. During secure application loading, an encrypted application is transferred from on-board flash memory to external double data rate synchronous dynamic random access memory (DDR-SDRAM) via a microprocessor. Following application loading, the core-based security technique provides both confidentiality and authentication for data stored in a microprocessor's system memory. The benefits of our low overhead memory protection approaches are demonstrated using four applications implemented in a field-programmable gate array (FPGA) in an embedded system prototyping platform. Each application requires a collection of tasks with varying memory security requirements. The configurable security core implemented on-chip inside the FPGA with the microprocessor allows for different memory security policies for different application tasks. An average memory saving of 63% is achieved for the four applications versus a uniform security approach. The lightweight circuitry included to support application loading from flash memory adds about 10% FPGA area overhead to the processor-based system and main memory security hardware.

The rapid growth of the Internet of Things (IoT) introduces significant security risks, including unauthorized access, data breaches, and supply chain attacks. Traditional models like Role-Based Access Control (RBAC) lack scalability and realtime enforcement for dynamic IoT environments. This paper presents the MQTT-ZT Secure Broker—an MQTT-based IoT communication framework built on Zero Trust Architecture (ZTA). It integrates Attribute-Based Access Control (ABAC) directly into the broker using a built-in Policy Enforcement Point (PEP) and Axiomatics’ ALFA policy engine for efficient, low-latency authorization. Experiments conducted in a cyber range show the broker maintains low processing times—20–79 ms for publishers and $\mathbf{2 4 - 6 3 ~ m s}$ for subscribers—even at $\mathbf{2 0 0}$ clients, outperforming traditional methods that often exceed 100 ms. These results highlight the architecture’s ability to scale while ensuring continuous verification and minimal latency. The MQTT-ZT Secure Broker offers a robust and scalable Zero Trust solution for securing IoT environments.

In this paper, we present a new 3D wirelength distribution model which considers the contribution of through-silicon-via (TSV) on wirelength, die area, and power consumption. Since TSVs occupy the device layer together with active devices, the die area increases if TSVs are utilized. This area overhead, which in turn affects the wirelength, worsens due to the large size of TSVs themselves, which is shown to be as large as logic gates themselves. Moreover, the capacitive coupling among TSVs and wires cause non-negligible amount of parasitic capacitance, which worsens power consumption. We present and validate a new 3D wirelength distribution and power consumption model to correctly model the various impacts of TSV.