SFDR considerations for current steering high-speed digital to analog converters

A 600-MS/s 6-bit folding and interpolation analog-to digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. Under a supply voltage of 1.4 V, the ADC achieves 5.55 bit of effective number of bits (ENOB) and 47.84 dB of spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with 500-Ms/s sampling rate and achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with 600-Ms/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 0.66 LSB, respectively. The circuit is prototyped in 0.13-µm CMOS process and occupies a core area of 0.17 mm2. The converter only dissipates 25 mW1.

Conventionally, source followers have been used at the block of track-and-hold amplifiers (THA) for highspeed medium-bit analog-to-digital converters (ADCs). Even though the input signals of an ADC are fully differential, two single-ended source followers should be normally used. This is because differential source followers have some drawbacks. In this study, a wideband fully differential source follower is presented to obtain maximum efficiency of a fully differential THA. Because a cross coupling technique at the differential nodes is adopted, the performance of the proposed source follower is superior to the performance of conventional followers. The result of Spurious Free Dynamic Range(SFDR) is -66.92dBc for F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> =F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> /2 at F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> =500MHz. The SFDR of the proposed source follower is better by about 8.6dB than the SFDR of a conventional source follower under the same experimental conditions. To verify them, an 8-b cascaded folding ADC which includes the proposed source follower is fabricated with a 0.13um CMOS technology.

Modern wireless communication standards that support high rates of voice and video streaming need high-speed Analog-to-Digital Converters (ADCs) with wide Spurious-Free Dynamic Range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method based on this analysis to randomize the mismatches among the ADC channels. Analyses and simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution, channel's number and sampling rate. For a 10-bit 500 MS/s ADC, the SFDR achieved using the proposed randomizing method can be as wide as 75 dB, which is an enhancement of more than 26 dB comparing to the conventional time interleaved ADC.

This paper presents a high-resolution, area- and power-efficient successive approximate register (SAR) analog-to-digital converter (ADC) for high precision nerve recording. The design features a new “half-split” feedback digital-to-analog converter (DAC) capacitor array with integrated digital calibrations, which allow automatic estimation and calibration of capacitor mismatches. As a result, the SAR ADC precision can be substantially improved given the constraints on circuits area and power consumption. The design has been fabricated in a 0.13μm CMOS process with a core area of 0.17mm2 (280μm×620μm). When measured at 40kSample/s, the ADC consumes 10μW of power and achieves a 72.7dB signal-to-noise-plus-distortion ratio (SNDR) and a 92.1dB spurious free dynamic range (SFDR) over the Nyquist bandwidth. Compared with the noncalibrated ADC, the proposed methods provide the improvements on SNDR, SFDR, and nonlinearity by 12.6dB, 22.7dB, and 4–6 times, respectively.

This brief presents a zero-crossing-based pipeline analog-todigital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13-μm CMOS process and occupies a die area of 0.7 mm2. The differential and integral nonlinearity of the ADC are less than 0.83/-0.47 and 1.05/-0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm2.

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with 0.18μm complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

This paper presents an 8-bit 100KS/s successive approximation register (SAR) analog-to-digital convertor (ADC) in SMIC 0.13 µm 1P8M process for biomedical applications. This ADC is implemented with sub-circuits consuming no static power, thereby preserving the desired low power characteristic. According to the measured results, the SAR ADC has a signal-to-noise distortion ratio (SNDR) of 49.2 dB, and the spurious free dynamic range (SFDR) of 63 dB for a 9.37 kHz full-scale input sinusoidal wave at a 100 kHz sampling rate. The effective number of bit (ENOB) is 7.8 bits. The differential nonlinearity (DNL) is in the range of −0.15/+0.15 LSB whereas the integral nonlinearity (INL) is within −0.35/+0.23 LSB. The total power is 3.2uW and the figure of merit (FOM) is 143 fJ/conversion-step.

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic comparators are used to save more ADC power consumption. Their accuracy is improved by the proposed pseudodifferential offset calibration loop. The digital-sub-R also helps to reduce the dynamic offset of the fine comparators caused by the input common-mode variation. Fabricated using a 55-nm CMOS technology, the reported 8-bit 1-GS/s ADC consumes only 16 mW from a 1.2 V supply. Measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 46 and 55 dB, respectively. Measured effective number of bits (ENOB) is seven bits at 10-MHz input frequency. At Nyquist input, the ENOB performance of 6.3 bits is still maintained. Its figure-of-merit is 197-fJ/conversion-step.

A 14-bit digitally calibrated digital-to-analog converter (DAC) is presented. This DAC uses a simple current comparator for the current measurement during calibration instead of a high-resolution ADC. Therefore, compared to a calibration scheme utilizing a high-resolution ADC, a faster calibration cycle is possible with smaller additional circuits. To reduce the additional area for calibration and error compensation, the lowest 8-bit DAC is used for both error correction and for normal operation; the additional DACs required for calibration are only of 3-bit and of 7-bit resolution. Nevertheless, a large calibration range is attained. Full 14-bit resolution is achieved on a small chip-area (0.72 mm2). The measurement results show that the spurious free dynamic range is 83.4 (46.6) dBc for signals of 6 kHz (30 MHz) at an update rate of 100 MS/s.

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter (ADC) is presented. This ADC with single track-and-hold (T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers. The prototype ADC achieves 5.55 bits of the effective number of bits (ENOB) and 47.84 dB of the spurious free dynamic range (SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with a 600-MS/s sampling rate. This ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm2 in the 0.13-μm CMOS process.

A low power 10-bit 125-MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) based on MOS bucket-brigade devices (BBDs) is presented. A PVT insensitive boosted charge transfer (BCT) that is able to reject the charge error induced by PVT variations is proposed. With the proposed BCT, the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably. The prototype ADC based on the proposed BCT is realized in a 0.18 μm CMOS process, with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm2. The prototype ADC achieves a spurious free dynamic range (SFDR) of 67.7 dB, a signal-to-noise ratio (SNDR) of 57.3 dB, and an effective number of bits (ENOB) of 9.0 for a 3.79 MHz input at full sampling rate. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.5/−0.3 LSB and +0.7/−0.55 LSB, respectively.