SI for free: machine learning of interconnect coupling delay and transition effects

We describe a procedure based on an existing static timing analysis tool for selecting path delay faults to target during test generation. The use of an existing static timing analysis tool ensures that a state-of-the-art process can be used for estimating path delays. However, static timing analysis, by itself, can be inaccurate as it does not take into consideration conditions that are necessary for detecting path delay faults. In the proposed method, these conditions are captured as what are called input necessary assignments, which static timing analysis tools are able to use. By providing the static timing analysis process with the input necessary assignments for a selected path, the static timing analysis process can estimate the delay of the path more accurately. It can also identify additional paths whose delays are at least as high as those of the selected paths. Thus, feeding back the input necessary assignments to the static timing analysis process enhances the correlation between static timing analysis and actual timing of tests on silicon. The result is a set of potentially detectable path delay faults associated with critical paths based on more accurate estimates of the path delays that can be exhibited by a test set, compared with the set that would be obtained by static timing analysis alone.

Recent static timing analysis (STA) tools have utilized task dependency graph (TDG) parallelism to enhance the STA runtime performance. Although TDG parallelism shows promising speedup, the overhead of scheduling a TDG can become dominant as the TDG becomes larger. To minimize the scheduling overhead, several TDG partitioning algorithms have been proposed to reduce the TDG size without affecting its task parallelism. Despite improved performance, existing TDG partitioners all fall short of incremental partitioning, limiting their practical use in STA tools that support timing-driven operations. To overcome this limitation, we propose iTAP, an incremental TDG partitioner to fully leverage the power of TDG partitioning in task-parallel STA applications. Compared to a state-of-the-art full TDG partitioner, iTAP enhances the overall STA performance by up to 2.97×.

Superconducting single-flux-quantum (SFQ) technology is a beyond-complementary metal–oxide–semiconductor (CMOS) technology, promising ultrahigh processing speed and low power consumption. A timing analysis tool for SFQ circuits should check circuit timing behavior, including working frequencies and hold time violations to determine the circuit performance. Unlike CMOS gates, generic SFQ gates are clocked gates, which produce their output pulses in response to a clock pulse and have a fan-out capability of one. An SFQ splitter, a special clockless gate that has a fan-out capability of two, is used to address the fan-out limitation. This gate is also utilized in the clock tree, which distributes clock pulses to various SFQ gates. The delay of a clock path in a clock tree is determined by the wire delays of connection nets and gate delays of splitters. However, the splitter delays in a clock path are significantly affected by process variations, resulting in a challenging skew problem. Furthermore, existing timing analysis tools of SFQ circuits are developed based on the timing definitions, rules, and constraints from CMOS technology with very few modifications. This article demonstrates the incompleteness of the existing SFQ technology timing definitions. Precisely, it presents a novel static timing analysis (STA) tool, qSTA, which checks the timing behavior of SFQ circuits based on revised definitions of the setup time and hold times. qSTA encompasses the common path pessimism removal technique, which removes the delays of the shared path segments between two clock paths to achieve a better approximation of real skew values. qSTA takes only 5.33 s to check the timing behavior of a 16-bit integer divider with 36 732 gates and 55 939 nets.

Path tracing is a key requirement in providing various functionalities in a Static Timing Analysis (STA) tool. With growing design sizes and advancements in STA techniques like statistical timing analysis, path tracing techniques need to be more efficient and accurate. Naive extensions of path tracing techniques for statistical timing analysis are found to be inefficient and inaccurate. In this paper, we present a novel Statistical Path Tracing (SPT) approach and illustrate its application in Common Path Pessimism Removal (CPPR). We demonstrate that SPT is more efficient and accurate when compared to a Deterministic Path Tracing (DPT) approach.

High performance applications are highly affected by process variations due to considerable spread in their expected frequencies after fabrication. Typically ldquobinningrdquo is applied to those chips that are not meeting their performance requirement after fabrication. Using binning, such failing chips are sold at a loss (e.g., proportional to the degree that they are failing their performance requirement). This paper discusses a gate-sizing algorithm to minimize ldquoyield-lossrdquo associated with binning. We propose a binning yield-loss function as a suitable objective to be minimized. We show this objective is convex with respect to the size variables and consequently can be optimally and efficiently solved. These contributions are yet made without making any specific assumptions about the sources of variability or how they are modeled. We show computation of the binning yield-loss can be done via any desired statistical static timing analysis (SSTA) tool. The proposed technique is compared with a recently proposed sensitivity-based statistical sizer, a deterministic sizer with worst-case variability estimate, and a deterministic sizer with relaxed area constraint. We show consistent improvement compared to the sensitivity-based approach in quality of solution (final binning yield-loss value) as well as huge run-time gain. Moreover, we show that a deterministic sizer with a relaxed area constraint will also result in reasonably good binning yield-loss values for the extra area overhead.

Statistical static timing analysis (SSTA) tools have mostly addressed the process variations of devices and lumped interconnect RC effects. This paper provides an overview of interconnect process variations of capacitive coupling and its effect on crosstalk delay and noise. The correlations among parallel plate, lateral and total capacitance is shown. Correlations between resistance and capacitance are illustrated to enable development of a simple and efficient model for delay and noise analysis. Experimental results are shown to validate the assumptions on the linearity of sensitivity of delay and noise to process variations. A methodology to account for process variations in crosstalk delay and noise is proposed.

The purpose of this study was to explore the diagnostic value of the arrival time difference between lesions and surrounding lung tissue on contrast-enhanced sonography of subpleural pulmonary lesions. A total of 110 patients with subpleural pulmonary lesions who underwent both conventional and contrast-enhanced sonography and had a definite diagnosis were enrolled. After contrast agent injection, the arrival times in the lesion, lung, and chest wall were recorded. The arrival time differences between various tissues were also calculated. Statistical analysis showed a significant difference in the lesion arrival time, the arrival time difference between the lesion and lung, and the arrival time difference between the chest wall and lesion (all P < .001) for benign and malignant lesions. Receiver operating characteristic curve analysis revealed that the optimal diagnostic criterion was the arrival time difference between the lesion and lung, and that the best cutoff point was 2.5 seconds (later arrival signified malignancy). This new diagnostic criterion showed superior diagnostic accuracy (97.1%) compared to conventional diagnostic criteria. The individualized diagnostic method based on an arrival time comparison using contrast-enhanced sonography had high diagnostic accuracy (97.1%) with good feasibility and could provide useful diagnostic information for subpleural pulmonary lesions.

This paper presents the comparisons of error characteristics between time of arrival (TOA) and time difference of arrival (TDOA), especially the relationship between position estimates and their error covariance. The errors of pseudorange measurements are considered as weighted or correlated due to the constellations of satellite and environment of a user. It is analytically demonstrated that the error covariance matrix and position estimates for TDOA are the same as those for TOA.. It also shows that the error covariance for TDOA does not change regardless of any single difference operator.

Early RTL delay prediction using neural networks

As design size gets larger and becomes more complicated with feature integration, the runtime for Static Timing Analysis (STA) becomes more of a concern. Due to time-to-market pressure, the validation of the design is performed in parallel with the physical synthesis flow; therefore it is not uncommon to find last minute critical logic bugs during final design integration iterations. However, timing verification needs to be run on full-chip level to ensure that the check is comprehensive. This paper proposes a method to isolate only those logics which are affected by the Engineering Change Order (ECO) for STA. This simplification will allow faster ECO iteration to enable a more efficient timing convergence. The proposed method is also suitable to be used for multithreading in STA engines to speed-up timing verification due to ECO changes. Engineering Change Order (ECO), Static Timing Analysis (STA), Incremental Static Timing Analysis, VLSI design

Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for inter- and intra-die process variations and their spatial correlations. Since statistical timing analysis has an exponential run time complexity, we propose a method whereby a statistical bound on the probability distribution function of the exact circuit delay is computed with linear run time. First, we develop a model for representing inter- and intra-die variations and their spatial correlations. Using this model, we then show how gate delays and arrival times can be represented as a sum of components, such that the correlation information between arrival times and gate delays is preserved. We then show how arrival times are propagated and merged in the circuit to obtain an arrival time distribution that is an upper bound on the distribution of the exact circuit delay. We prove the correctness of the bound and also show how the bound can be improved by propagating multiple arrival times. The proposed algorithms were implemented and tested on a set of benchmark circuits under several process variation scenarios. The results were compared with Monte Carlo simulation and show an accuracy of 3.32% on average over all test cases.

MLAT (Multilateration) is becoming one of the leading surveillance techniques in the A-SMGCS (Advanced - Surface Movement Guidance & Control System), and play an important role in the future's tracking system. MLAT is based on the TDOA (Time Difference of Arrival). It is very important for MLAT to associate TOAs (Time of Arrival) from different ground stations. This paper designs an improved clustering method with elastic grouping logic to adaptively associate the TOAs. This method dynamically adjusts the group number based on the cost function. Experiment results show our improved method can not only increase correct association ratio, but also decrease the position error of MLAT.

Late-arriving barn swallows linked to population declines

Recently, indoor positioning has been one of the hot topics in the field of navigation and positioning. Among different solutions on indoor positioning, positioning with acoustic signals has its promise due to its relatively high accuracy in the line of sight scenarios, low cost, and ease of being implemented in smartphones. In this work, a novel acoustic positioning method, called RATBILS, is proposed, in which encoded chirp acoustic signals are modulated and transmitted by different acoustic base stations. The smartphones receive the signals and perform the following three steps: (1) preprocessing; (2) time of arrival (TOA) estimation; and (3) time difference of arrival (TDOA) calculation and location estimation. In the preprocessing stage, we use band pass filters to filter out low-frequency noise from the environment. At the same time, we perform a signal decoding function in order to lock onto the positioning source. In the TOA estimation stage, we conduct both coarse and fine detection to enhance the accuracy and robustness of TOA estimation. The primary goal of coarse detection is to establish a noise range for fine detection. The main objective of fine detection is to emphasize the intensity of the first arrival diameter and resistance with multipath and non-line-of-sight (NLOS) caused by human body obstruction. In the TDOA calculation and location estimation stage, we estimate the TDOA based on the TOA estimation and then use the TDOA results for position estimation. In order to evaluate the performance of the proposed RATBILS system, two indoor field tests are carried out. The test results show that the RATBILS system achieves a positioning error of 0.23 m at 92% in region 1 of scene 1 and is superior to the traditional threshold method. The RATBILS system achieves a positioning error of 0.56 m at 92% in region 2 of scene 1 and is superior to the traditional threshold method. In scene 2, the maximum average positioning error was 1.26 m, which is better than the 3.33 m and 3.87 m of the two traditional threshold methods.

Received Signal Strength Indicator (RSSI) is simplest among various indoor localization methods. The main drawback is requiring a training phase to build fingerprints database, which is time consuming and sensitive to changes of test environment. Time based approaches such as Time of Arrival (ToA) and Time Difference of Arrival (TDoA) achieve better performance with some hardware expenditure, while location accuracy is significantly affected by multipath interference. By employing Super-resolution techniques (SRTs), multipath components can be estimated to improve localization precision, but limited to OFDM-based Multiple Input Multiple output (MIMO) wireless communication systems. Considering for general radio signals with strong correlation, we propose an enhanced TDoA approach based on RSS-assisted cross-correlation method. Simulation and experimental results demonstrate that our method is effective to mitigate multipath interference, verified by IEEE 802.11b WLAN. Compared with SRTs, our method achieves comparable localization precision, and has superiority in computational complexity and anti-noise performance.