Si top corner damage-free etch process for shallow trench isolation

Hot-carrier stresses were performed on n-MOS transistors with LOCOS and shallow trench isolation. For transistors stressed under the different damage creation conditions, no discernible difference in lifetimes was found for devices down to W/L=3/0.45 mu m. It is shown, however, that the edge of the trench isolation (0.1 mu m wide) is more sensitive to hot carrier effects, having a lifetime up to four times less than the center of the channel. For devices with a W/L ratio of two or less, this could prove problematic. It could also have repercussions for transistors under high-gate-field (Fowler-Nordheim) conditions. >

Optimization of a 3.3-V/ 5.0-V tolerant electrostatic discharge (ESD) protection network for both diffused n-well/LOCOS and retrograde well/shallow trench isolation (STI) CMOS technologies in a RISC microprocessor is discussed. ESD-related semiconductor-process key design features, ESD circuit operation, data, simulation and failure analysis are presented. ESD robustness of 4000-V human body model (HBM), 400-V machine model (MM), and 1500-V charge device model (CDM) is achieved in both technologies using a common design. >

With the aid of the thermal-electrical model of the 0.12μm SiGe heterojunction bipolar transistor (HBT) with shallow trench isolation (STI), the transient thermal behavior of the device is studied. Both thermal time constant (τ) and thermal capacitance (C TH ) are adopted to represent the transient thermal behavior. Furthermore, the influence of pulse power, thickness and depth of shallow trench isolation on τ and C TH are studied. It is shown that both τ and C TH are increased with the increase of pulse power. With the increase of shallow trench thickness (t s ), τ is almost increased linearly, which leads to the prolongation of time to reach thermal steady-state for STI device. At the same time, with the increase of shallow trench depth (d s ), C TH is decreased obviously, which leads to the weakness of ability to store heat of HBT with STI. In addition, τ is increased slightly with the increase of d s and C TH is insensitive to variation of t s . The results above shed light on the improvement of the transient thermal behavior of shallow trench-isolated SiGe HBTs.

Radiation enhanced drain induced barrier lowering (DIBL) was experimentally observed and verified by 3D simulations for submicron devices with trench isolation oxides. Submicron MOSFETs with shallow trench isolation were exposed to total-ionizing-dose radiation. Prior to irradiation, the devices exhibited near-ideal current-voltage characteristics, with no significant short-channel effects for as-drawn gate lengths of 0.4 /spl mu/m. Following irradiation, the off-state leakage current increased significantly for total doses above about 650 krad(SiO/sub 2/). In addition, the irradiated devices exhibited DIBL that increased the drain current by 5-10/spl times/ for a gate length of 0.4 /spl mu/m (the nominal minimum gate length for this process) and much more for slightly shorter devices (0.35 /spl mu/m). The increase in the off-state leakage current and the accompanying DIBL are shown to be associated with a parasitic field-effect transistor that is present at the edge of the shallow trench. Three-dimensional simulations are used to illustrate the effect. Simulations show that trapped charge at the trench sidewalls enhances the DIBL by depleting the edges of the channel. Radiation-induced charge may decrease the effectiveness of short-channel engineering.

Ultrathin DPN STI SiON liner for 40nm low-power CMOS technology

As the strained engineering technology of metal-oxide-semiconductor field effect transistors (MOSFET) is scaled beyond the 22 nm node critical dimension, shallow trench isolation (STI) becomes one of the most important resolutions for isolate devices to enhance the carrier mobility of advanced transistors. Several key design factors of n-type MOSFET (NMOSFET) under the resultant loadings of STI structures and contact etching stop layers are sensitively analyzed for silicon channel stress via finite element method-based simulations integrated with the use of design of experienmnts. NMOSFETs with 15 nm deep sunken STI have achieved a ~5% mobility enhancement as compared with a regular STI shape. By adopting simulation-based factorial designs, we have determined that the design factor of recess depth in STI is a critical factor influencing device performance. Moreover, a response surface curve on carrier mobility of NMOSFET under a consideration of combining the sunken STI and source/drain lengths is further presented in this research.

The impact of capacitive coupling effects increases with scaling down the dimensions and towards higher performances. For bipolar technologies, the introduction of deep trench isolation gives a substantial reduction in the collector substrate capacitance. In this paper a method for the formation of airgap deep trenches (with 1μm – depth 6 μm) is presented. The method is fully compatible with standard CMOS Shallow Trench Isolation (STI) and does not require additional masking steps. The approach is based on a partial removal of the poly-Si filling in the trench. Subsequently, inside D-shape oxide spacers are formed narrowing the opening of the trench down. An SF6 plasma is used to convert the nearly completely incorporated poly-Si to volatile SiF4, such that it desorbs through the opening. In the following steps the opening is sealed by depositing SiO2 resulting in the formation of an airgap (patent pending). The normal module for STI formation continues without any adaptation of the process steps. In total four standard additional process steps are needed.The absence of the common oxide/poly filling in the deep trench decreases the peripheral collector substrate capacitance with an order of magnitude to a value of 0.02fF/μm. As a consequence the low power available bandwidth is improved with 90%.

Shallow trench isolation (STI) and active area (AA) top cornerrounding is important to device performance. AA top cornerrounding techniques include STI etch [1], linear oxidation [2], H2annealing [3] and wet oxide pull back (PB). However,conventional STI etch will caused AA facet and needs additionalthermal in liner oxidation or H2 annealing processes. Wet oxide PBeasily controls the pad oxide etching amount and reaches thedesired AA top corner top rounding radius. In this study, differentpad oxide PB was achieved by hydrogen fluoride (HF) etching andcorrelated with corner rounding. For high pad oxide PB, additionalhydrogen peroxide (H2O2) with dilute HF (DHF) can optimize theAA top corner profile and enlarge the corner radius.

This paper presents the effect of shallow trench isolation (STI) on the dark count rate (DCR) and after-pulsing probability (APP) of deep-junction-based single-photon avalanche diodes (SPADs). Two different SPADs were fabricated in 110 nm CMOS image sensor technology, one with STI and the other without STI between its anode and cathode. With TCAD simulations and measurements, we have clearly demonstrated that the SPAD without STI enables a dramatic decrease in DCR by more than three orders of magnitude without suffering from the lateral leakage current between the anode and cathode. By excluding the STI from the device, the proposed SPAD also achieves a negligible APP while the SPAD with STI shows a very high APP of 92%. Thanks to the low-noise performance, the proposed SPAD becomes operable with higher excess bias voltage so that it achieves good photon detection probability, 58.3% at 500 nm and 3% at 940 nm, and timing jitter, 71 ps full width at half maximum at 670 nm, when the reverse bias voltage is 17 V.

The noise behaviors of the junction field-effect transistor (JFET) fabricated with self-aligned planer technology are studied. The device structure being considered has a wide separation between source-gate and drain-gate with a shallow trench isolation (STI) technique. High noise level is found in the devices with STI and the normalized drain noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated in the STI regions and a model is developed to explain the bias dependence of the noise characteristics. To reduce the noise level, the STI region should be kept small and better oxidation technique should be employed for the STI passivation.

Because it minimizes the spaces between transistors, the aspect ratio of shallow trench isolation (STI) becomes large and it gets difficult to fill STI by conventional LP-CVD TEOS SiO/sub 2/ film without void formation. A high-density plasma deposition process has been evaluated for better STI fill instead of LP-CVD, however, the new equipment costs more than that for LP-CVD. This paper describes a new technique, a pulse pressure chemical vapor deposition (CVD) method for STI fill without forming any voids by using conventional LP-CVD equipment. Pulse pressure enables a uniform source gas supply to the STI trench and a conformal film deposition without voids.

Starting at the 65 nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source - shallow trench isolation - has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that enables the exploitation of STI stress for performance improvement of standard cells and custom integrated circuits. We start with process simulation of a 65 nm STI technology, and generate mobility models for STI stress based on these simulations. Based on these models, we are able to perform STI stress-aware modeling and simulation using SPICE. We then present our optimization of STI stress in standard-cell and custom designs using active-layer (dummy) fill insertion to alter the STI widths. Circuit level experimental results are based on a miscellaneous ring oscillator, which is known to correlate well to silicon. Using a generic 65 nm cell library, we show that the STI-optimized designs provide up to 8% improvement in clock frequency. The frequency improvement through exploitation of STI stress comes at practically zero cost with respect to area and wire length.

In this work, a novel ultra high-voltage LDMOS device structure design is presented by multiple local RESURF enhancement technology to achieve breakdown voltage up to 500-700V as well as low on-state resistance. This innovative LDMOS structure is realized by using discontinuous shallow trench isolation (STI) in the P-top region which is located on the surface of the n-type drift region, while there is remaining n-type drift regions between the discontinuous STI above the P-top, thus the multiple n-p-n-p junction in the vertical direction is formed as the multiple local RESURF enhancement. The optimal charge balance and discontinuous STI geometrical design are investigated by 2D Sentaurus TCAD process and device simulators. Compared to the conventional RESURF structures, the electrical field of this presented device shows multiple equivalent peaks caused by local RESURF enhancement between every two adjacent disconnected STIs instead of a single strong peak, therefore the integrated electrical field with respect to depletion area, or the breakdown voltage, is greater. This allows the demonstration of better BVdss-Ron, sp trade-off as the power device figure of merit. Furthermore, this novel LDMOS structure can be manufactured by conventional active-area (AA) process without any additional fabrication cost.

The impact of shallow trench isolation (STI) on the statistical variability introduced by random discrete dopants and trapped interface charge is clarified for the first time using 3-D statistical numerical simulations. The possible influence of the STI on the p-n junction shape is also taken into account. The simulated test bed devices are contemporary 35-nm gate-length high-performance nMOSFETs typical for the 45-nm technology generation. In transistors with straight junction edges, the STI-related fringing effects increase the equivalent channel width, reducing the statistical variability. Changes in the junction shape in the STI vicinity can further reduce or increase the variability.

The effective hole mobility of long strained Ge pFinFETs, fabricated with shallow trench isolation (STI) first and last approaches, is systematically evaluated from room temperature down to 77 K, from planar-like (100 nm) to narrow (20 nm) devices. The goal is to identify the dominant scattering mechanism. Here, the split capacitance-voltage (CV) technique has been applied, based on combined current–voltage (I–V) and CV measurements. It is shown that even at 77 K, the phonon scattering mechanism dominates the STI last process, while the Coulomb scattering strongly affects the STI first approach. On the other hand, the latter shows slightly higher hole mobility compared to the STI last counterpart.