Silicon Carbide Junction Field‐Effect Transistors (SiCJFETs)

Buried-gate junction field-effect transistors (JFETs) have been fabricated in 4H polytype silicon carbide (SiC). The dynamic switching characteristics of the JFETs in a circuit with inductive load ...

Analytical model for I- V characteristics of JFETs with heavily doped channels

This paper presents the system for the evaluation of operation of a depletion-mode silicon carbide (SiC) power junction field-effect transistor (JFET). The main part of the system is a dc-dc step-down converter which represents realistic operating conditions for the switching devices in a synchronous buck configuration. In order to test the importance of the dead-time value on the operation and efficiency of the synchronous buck converter, a precise two-channel time-delay pulse signal generator is developed and its operation is described. The ability to precisely regulate control signal parameters of the high-side FET and low-side FET (switching voltage and current, operating frequency, duty cycle, dead-times, etc.) is needed in order to fully characterise SiC power switches. The functionality of the complete system is verified by measurements performed under various operating conditions.

With evolving landscape of DC power transmission and distribution, a reliable and fast protection against faults is critical, especially for medium- and high-voltage applications. Thus, solid-state circuit breakers (SSCB), consisting of cascaded silicon carbide (SiC) junction field-effect transistors (JFET), utilize the intrinsic normally-ON characteristic along with their low ON-resistance. This approach provides an efficient and robust protection solution from detrimental short-circuit events. However, for applications that require high-voltage blocking capability, a proper number of JFETs need be connected in series to achieve the desired blocking voltage rating. Ensuring equal voltage balancing across the JFETs during the switching transitions as well as the blocking stage is critical and hence, this paper presents a novel passive balancing network for series connected JFETs for DC SSCB applications. The dynamic voltage balancing network to synchronize both the turn ON and OFF intervals is described analytically. Moreover, the static voltage balancing network is implemented to establish equal sharing of the total blocking voltage across the series connection of JFETs. The proposed dynamic and steady-state balancing networks are validated by SPICE simulation and experimental results.

In specialized fields such as fusion energy, aerospace, and nuclear power, radiation detectors are often required to operate reliably at high temperatures. Wide-bandgap semiconductors offer a promising pathway for developing more compact, sensitive, and high-precision detection systems. However, conventional silicon-based preamplifiers suffer from performance degradation and increased noise under elevated temperatures, limiting the effectiveness of these advanced detectors. Silicon carbide (SiC) devices present a compelling alternative for realizing high-temperature, low-noise preamplifiers. This study investigates the electrical output characteristics and noise performance of SiC-based junction field-effect transistors (JFETs) at high temperatures. Due to the intrinsic properties of SiC—such as its wide bandgap and incomplete ionization—simply substituting silicon with SiC in an identical structure does not achieve optimal results. Building on prior research, this work systematically explores how JFET structural design influences device performance by comparing the electrical characteristics and output noise of devices with varying channel parameters across a range of temperatures. The results highlight the effects of channel doping concentration and channel height on transconductance and equivalent output noise under high-temperature conditions, offering valuable design guidance for low-noise, high-temperature SiC-JFETs. Furthermore, this paper presents the experimental fabrication and performance evaluation of SiC-JFETs specifically designed for front-end circuits in nuclear electronics. Key electrical parameters are analyzed as functions of temperature. These findings provide a foundation for advancing SiC-JFET-based front-end electronics in nuclear detection systems.

Extraction method of interfacial injected charges for SiC power MOSFETs

We examine a time-dependent, three-dimensional rotation of magnetic ellipsoidal particles in a two-dimensional, simple shear flow and a uniform magnetic field. We consider that the particles have paramagnetic and ferromagnetic properties, and we compare their rotational dynamics due to the strengths and directions of the applied uniform magnetic field. We determine the critical magnetic field strength that can pin the particles’ rotations. Above the critical field strength, the particles’ stable steady angles were determined. In a weak magnetic regime (below the critical field strength), a paramagnetic particle’s polar angle will oscillate toward the magnetic field plane while its azimuthal angle will execute periodic rotations. A ferromagnetic particle’s rotation depends on its initial angles and the magnetic field strength and direction. Even when it is exposed to a critical magnetic field strength, its rotational dynamics will either be pinned in or out of the magnetic field plane. In a weak magnetic regime, a ferromagnetic particle will either execute out-of-plane rotations or will oscillate toward the magnetic field plane and perform periodic rotations. For both particles, we analytically determine the peaks and troughs of their oscillations and study their time-dependent rotations through analytical and numerical analyses.

Current oscillation of Silicon Carbide (SiC) based Junction Field-Effect Transistor (JFET) Bi-Directional Switches (BDSs) during turn-on transient has an impact on the stability and reliability of power electronic conversion systems. Proper handling of the current oscillation during turn-on transient is suitable to exploit the full potential of fast SiC JFET BDSs. In this paper one method is proposed to damp the current oscillation, namely, paralleling a snubber capacitor (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J</sub> ) with JFET in power loop. Equivalent and simplified circuit models considering all parasitic elements for SiC JFET BDSs for the turn-on condition are presented. Simple analytic expression is introduced to provide the theoretical analysis of the switching oscillation phenomenon, and to guide the optimal value of snubber capacitor. Experimental results validate the effectiveness of the proposed method.

This paper compares the conducted electromagnetic interference (EMI) in Si insulated gate bipolar transistor (IGBT) and silicon carbide (SiC) junction field-effect transistor (JFET) based motor drives. Two inverters, with the SiC and Si transistors, respectively, are built using the same circuit layout and investigated accordingly. Their conducted EMI levels are compared under the conditions of without filter and with traditional common mode (CM) filters. Reasons of the exhibited different noise emissions are analyzed. To verify the discussions, two inverters are tested in the CM. This allows for the identification and analysis of their maximized CM and differential mode (DM) wave shapes. It is shown that the excited parasitic oscillations during the switching transients are magnified more in the SiC JFET inverter, which is the main cause of the noise difference. Lastly, improved filtering solutions are proposed, which effectively suppressed the increased high-frequency noise due to the faster SiC switching speed.

Compared with Si devices, wide bandgap (WBG) devices will cause more serious electromagnetic interference (EMI) problems due to their fast switching speeds. In order to better compare and predict their EMI, this article proposes an improved mathematical modeling method to calculate the EMI spectrum envelope. It is based on an accurate time-domain decomposition of switching transient behavior together with a frequency-domain calculation. Detailed EMI spectrum envelope analytic expressions are derived with full consideration of Miller platform (MP), reverse conduction (RC), and ringing effects, while traditional calculation mainly focused on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">du/dt</i> . The proposed mathematical modeling method has been applied to Si, silicon carbide (SiC), and gallium nitride (GaN) devices, respectively, and verified by comparing calculated and simulated results. In order to further verify this method, double-pulse test circuits of Si, SiC, emode GaN, and cascade GaN are built, and CM and DM EMI are also compared. The result reveals that, compared with Si devices, the MP, RC, and ringing effects of WBG devices have more serious effects on EMI.

Wide bandgap materials such as Silicon Carbide (SiC) has enabled the use of medium voltage unipolar devices like Metal-Oxide Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs), which can switch at much higher frequencies as compared to their silicon counterparts. It is therefore imperative to evaluate the performance of these medium voltage devices. In this paper, the static characterization and the switching performance of the new single die 3.3 kV, 45 A 4H-SiC MOSFET developed by Cree Inc are presented. The switching performance is measured through the conventional Double Pulse Test. Testing is done at a dc-link voltage of 1.5 kV for different values of current, and gate resistances.

The phenomenon of partial discharge of soil that occurs when a lightning current enters the ground through a ground electrode poses a threat to the safety of personnel and equipment. The strength of partial discharge and the formation of soil discharge channels are closely related to the magnitude of the critical breakdown field strength. Therefore, how to accurately obtain the variation law of the critical breakdown field strength of typical soil is the key to realize the safe operation of the grounding device and the cable in the ground and ensure the safety of personnel and equipment. In this paper, a simulation experiment of soil impact characteristics is used to study the variation law of typical soil critical breakdown field strength with soil properties. X-ray transmission imaging technology is used to obtain the morphology of the discharge channel, and its non-intrusive observation method will not disturb the discharge channel itself, making the measurement more accurate. This paper first selects a variety of typical soils to study the influence of soil moisture, salt content, compactness and other factors on the discharge channel morphology, and then studies the calculation method of the critical breakdown field strength of the soil under different discharge channel morphologies. And further explore the reasons for the influence of typical soil media factors on the critical breakdown field strength. The experimental results show that under the same conditions, the relationship between the critical breakdown field strength values of different soils is: Ec of sandy soil <; Ec of loam soil <; Ec of pastoral soil; It is precisely because of the different reasons that different factors of the soil medium affect the critical breakdown field strength, the content of water and air inside the soil and the conductivity of the soil are different, so that the variation law of the critical breakdown field strength is different.

Silicon carbide (SiC) junction field-effect transistor (JFET) based bi-directional switches (BDSs) have great potential in the construction of several power electronic circuits, including matrix converters, multi-level converters, solid state breakers, and so on. Parasitic oscillation in SiC JFET-based BDSs has direct impact on the stability and reliability of these circuits. Proper handling of parasitic oscillation becomes highly critical. This paper focuses on the parasitic oscillation suppression in SiC JFET-based BDSs. A parallel snubber capacitor or a series ferrite ring was often used to damp parasitic oscillation in switching circuits in the literature. However, conventionally, the snubber capacitance was obtained by time-consuming and labour-intensive trial-and-error methods. The main contribution of this study is to derive the simplified equivalent transient circuit of the SiC JFET-based BDS considering all parasitic elements and quantitatively define the reasonable range of the snubber capacitance. And the combined effect of the selected snubber capacitance and the selected ferrite ring is investigated. In the end, simulation and experimental results validate the effectiveness of the proposed method.

This research investigates the electro-thermal switching characteristics and lattice temperature profile of a two dimensional (2D) silicon carbide (4H-SiC polytype) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell under resistive switching using Silvaco ATLAS Technology Computer Aided Design (TCAD) physics based simulation software. Physics based models were included to account for recombination effects, bandgap narrowing, low field and high field mobility and lattice heating. The electro-thermal simulation was performed at an ambient lattice temperature of 300K. The device was simulated for 100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 1000 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> drain current densities using a 1 kHz 50% duty cycle gate signal consisting of two cycles and 1.6 kHz 80% duty cycle signal consisting of three cycles. The analysis of lattice temperature profile revealed the formation of thermal hot spots in the vicinity of the (Junction Field Effect Transistor) JFET region in the DMOSFET structure during the switching phase and at the edge of the channel during the conduction phase. The magnitude of temperature rise was dependent on the drain current density used during the simulation.

Silicon Carbide (SiC) Junction-Field Effect Transistors (JFETs) are attractive devices for power electronics. Their high temperature capability should allow them to operate with a reduced cooling system. However, experiments described in this paper conclude to the existence of runaway conditions in which these transistors will reach destructive temperatures.