Simplified Doherty power amplifier structures

ABSTRACTIn this article, we present a simplified Doherty power amplifier (DPA) architecture for the easy implementation of dual‐band operation. The proposed DPA structure eliminates the 35 Ω quarter wavelength impedance inverters used in the conventional DPAs by matching the output impedances of the carrier and peak amplifiers of the DPA to other values (e.g., 100 Ω). The electrical lengths of the offset line and the phase compensation line are carefully chosen to enhance the Doherty effect (high efficiency at back‐off power level) at two assigned frequency bands. Broadband matching networks are also designed to increase the operation bandwidths at the two designed bands. To prove the design concept, a dual‐band DPA is designed and measured. In the first frequency band (550–650 MHz), the designed DPA provides 60.6–76.3% drain efficiency (DE) at full output power, 46–54.9% DE at 6 dB of output power back‐off (OBO); in the second frequency band (950–1050 MHz), the designed DPA provides 51.4–61.2% DE at full output power, 35–38% DE at 6 dB of OBO. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:953–956, 2015

Doherty power amplifier (DPA) with high efficiency at the output power back off is highly demanded for modern wireless communication systems to achieve high data rates and reduce the power consumption and operation costs. This paper presents a new design strategy for enhancing DPA’s back-off efficiency. New design strategy called asymmetrical matching network is used to achieve asymmetric operation, which helps to compensate for the low power delivered by the peaking stage in the conventional DPA. The simulation results showed an enhancement in the back-off efficiency, where the proposed design is able toachieve 46-52% drain efficiency at 8 dB output power back-off while maintains high efficiency of 73-80 % at saturation over the designed bandwidth of 3.4-3.6 GHz. The proposed design is suitable for high efficiency sub-6 GHz fifth-generation wireless applications.<br /><div> </div>

An improved reconfigurable Doherty power amplifier (DPA) structure with extended bandwidth is presented. A traditional DPA structure is often used to expand the output power back-off (OBO) range by using three transistors, and the peaking amplifiers work in the same frequency band. In this modified structure, the carrier amplifier works in the whole frequency band of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{1}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{3}$ </tex-math></inline-formula> , and two peaking amplifiers work in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{1}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{2}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{2}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{3}$ </tex-math></inline-formula> , respectively ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{1} &lt; f_{2} &lt; f_{3}$ </tex-math></inline-formula> ). In addition, switches are applied in power divider and power combining networks in order to switch peaking amplifier between frequency bands. A 1.8–3.4-GHz DPA has been demonstrated utilizing such a modified structure, and the frequency band is divided into two parts, which are 1.8–2.7 GHz and 2.7–3.4 GHz. The measured results show that 7.2–11.2 dB of saturated gain, 42.2–43.9 dBm of peaking output power, 45%–62.3% and 36.7%–48.5% of drain efficiency at peaking power levels and 6-dB OBO are delivered.

In this article, a fully integrated dual-band gallium nitride (GaN) Doherty power amplifier (DPA) based on multi-resonant circuits (MRCs) is presented. A lumped T-type network in combination with the output capacitances of the main and auxiliary transistors is able to realize the quarter-wavelength transformer (QWT) in DPA, and its component values are totally decided by the operating frequency, given a certain characteristic impedance. MRCs are proposed to exhibit the required component values at two different frequencies. By replacing each component in the T-type network with an MRC, a dual-band QWT can be achieved. An integrated dual-band DPA is implemented in a commercial 0.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaN-HEMT process to validate the proposed method. The fabricated DPA shows a saturated output power of 43.8–44.7/44.4–44.8 dBm, a 6-dB back-off drain efficiency (DE) of 41%–46%/41.5%–47%, and a saturated DE of 49%–52%/56%–59% in 3.35–3.6/4.8–5.2 GHz, with a compact size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times3.5$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Applying a 100-MHz OFDM signal with a 7.8-dB peak-to-average power ratio (PAPR), an average efficiency of 37%/40% and an average power of 37/37 dBm are measured at 3.5/5.0 GHz, and the adjacent channel power ratio (ACPR) is better than −49 dBc after digital predistortion (DPD). To the best of our knowledge, the proposed DPA is the first demonstration of fully integrated dual-band GaN DPAs.

This brief presents a three-way Doherty power amplifier (DPA) with a symmetric structure in terms of the output power capacities between the carrier and peaking amplifiers for high efficiency and linearity. Based on the analysis for the efficiency peak at the output power back-off, a symmetric structure was adopted to have higher overall efficiency for the modulated signal. Through the optimized bias condition for the two peaking amplifiers, the proposed three-way DPA can be linearized in the wide output power range. To validate the proposed scheme, a three-way DPA was designed and implemented using a 60 W GaN-HEMT for the carrier amplifier and two 30 W GaN-HEMTs for the peaking amplifiers. Using a 2.14 GHz long-term evolution downlink signal with a peak-to-average power ratio of 6.5 dB, the implemented symmetric three-way DPA exhibited a drain efficiency (DE) of 33.7% and an ACLR of -38 dBc at an average output power of 41.4 dBm. Compared to the condition with the same bias for the peaking amplifiers, the DE and average output power were improved by 8.0% and 2.4 dB for the given ACLR of -38 dBc, respectively.

This article presents a multimode Doherty power amplifier (M-DPA) monolithic microwave integrated circuit (MMIC). The M-DPA comprises of a load network (LN) based on a combination of current- and voltage-combining methods. By arranging the turn-on transitions of four parallel amplifiers based on the input power level, two carrier and two peaking amplifiers (2C2P) mode for 6-dB output power back-off (OBO) or one carrier and three peaking amplifiers (1C3P) mode for 12-dB OBO can be configured. The performances between efficiency and gain can be balanced according to the selected mode. The M-DPA concept was theoretically expanded to a generalized structure based on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> (or = <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{m}$ </tex-math></inline-formula> ) scalable amplifiers in parallel that were simply modeled as current sources. This generalized M-DPA supports <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N-1$ </tex-math></inline-formula> different operation modes with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> different OBO levels. For verification, the M-DPA MMIC was implemented using a 0.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gallium nitride (GAN)-HEMT process for 5G new radio (NR) applications (3.3–3.6-GHz band). Using a 5G NR downlink signal with a signal bandwidth of 100 MHz and a peak-to-average power ratio (PAPR) of 7.86 dB, at a frequency of 3.55 GHz, the drain efficiencies (DEs) of 37.7 and 33.8% and power gains of 8.3 and 6.4 dB were obtained for the 2C2P mode with an average output power of 37.0 dBm and for the 1C3P mode with an average output power of 31.0 dBm, respectively.

A Doherty power amplifier (DPA) using direct input power dividing circuit technology is discussed in this paper, which improves the AM-AM performance of the classical DPA. The proposed DPA is able to control the input power dividing ratio according to the input power, which results in the outputting ability of the peaking amplifier is increased dramatically. The ADS stimulation results show that the designed DPA based on two Freescale MRF6S27015 device achieve 51.9% drain efficiency and −33.6 dBc IMD3 when input long term evolution signal at 2.35 GHz and output power is 40.9 dBm, which improve 5.8% in drain efficiency and low 4dBc in IMD3 compared with classical DPA.

In this article, a novel high‐efficient Doherty power amplifier (DPA) is designed for linearity improvement from 2.1 to 2.4 GHz. The proposed DPA employs a pair of anti‐coupled lines loaded with a stepped impedance resonator to replace the λ/4 transmission line in the conventional DPA for harmonic suppression, phase compensation, and impedance transformation. The DPA is simulated, fabricated, and measured. As the measured results show, in the 2.1‐2.4 GHz band, the saturated output power is between 43.2 and 44.5 dBm with the saturated gain level between 10.2 and 11.5 dB. The saturated drain efficiency (DE) is between 60% and 70% with DE at 6 dB output power back‐off between 38% and 50%. Compared with the conventional DPA, the third‐order intermodulation distortion is reduced by 20 dB. The efficiency and gain have also been improved. The proposed DPA is feasible and applicable in modern wireless communication systems.

In this paper, we present the design of an ultracompact monolithic millimeter-wave integrated circuit Doherty power amplifier (DPA) using a novel reconfigurable input network at Ka -band. The proposed input network is formed by a compact broadside coupler and two additional field-effect transistors. By reconfiguring the relative phase offset between the main and auxiliary amplifiers, the DPA can be postoptimized to achieve high efficiency and maximal power gain flatness. More importantly, the DPA can be tuned for the highest performance at different frequencies. To verify the concept, a DPA is fabricated in a 0.15- $\mu \text{m}$ enhancement mode Gallium Arsenide (GaAs) process and exhibits a measured output power of 26.5 dBm and gain of 11.8 dB at 28 GHz. The peak power-added efficiency (PAE) is 42%, and the PAE at 6-dB output power backoff (PBO) is 31%, respectively. With reconfigurable capability, the DPA can maintain high performance over a 3-GHz frequency band from 26.5 to 29.5 GHz. To the best of the authors’ knowledge, the proposed DPA achieves among the highest backoff PAE over a wide bandwidth at Ka -band.

This letter presents the design of a broadband three-stage sequential Doherty power amplifier (DPA) with an octave bandwidth and a large high-efficiency range. The proposed DPA employs the sequential operation mode and a post-matching network (PMN) to expand the operating bandwidth and back-off range. Utilizing the three-stage sequential DPA structure, the design achieves broadband and high-efficiency performance at 10–12 dB output power backoff (OBO) across the entire 1.0–2.0 GHz band. A prototype of the three-stage sequential DPA has been fabricated using commercial gallium nitride (GaN) devices. Measurements demonstrate that the maximum output power ranges from 43.5 to 45.7 dBm, with drain efficiencies of 51.1%–67.1% at 10–12 dB OBO and 58.9%–72.9% at saturation throughout the design band, respectively. These results validate the effectiveness of the proposed circuit architecture and design strategy.

To achieve high efficiency at back-off output powers, a harmonic tuned Doherty power amplifier (DPA) using impedance buffer matching technique was presented for 5G applications. After obtaining the optimum fundamental and harmonic impedances using load-pull simulations, a harmonic control impedance matching network is proposed to design the output matching networks of the carrier and peaking amplifiers for high efficiency operation. To verify the proposed method, a 4.8-5.0 GHz highly efficient DPA was designed and measured. Measurement results show that the designed DPA has the saturated output power of higher than 41.5 dBm and the maximum efficiency is about 65%, while the efficiency at 6-dB back-off output power is higher than 50%. This method can enhance the back-off efficiency of the DPA effectively.

In this work, a Doherty power amplifier is presented for IMT-Advanced system at 450–470MHz frequency band. An imperfect Quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, is adopted to replace the bulky impedance inverter quarter-wave transmission line for designing the Doherty power amplifier (PA). Both the traditional and proposed structures for the Doherty power amplifiers were implemented. Comparing with the traditional Doherty amplifier, the size of the circuit and the manufacturing costs are decreased obviously. The measurement results of the proposed Doherty PA exhibit good performance as well as the traditional Doherty power amplifier. For a input signal with a 7.8dB Peak to Average Power Ratio (PAPR), the measured drain efficiency of the proposed Doherty power amplifier is 48.5% at an average output power of 43.0 dBm, which is a 7.8dB backed — off the peak output power. Moreover, in order to improve the linearity of the proposed Doherty power amplifier, the augmented Hammerstein and polynomial predistorter are used to linearize the proposed Doherty power amplifier. After digital predistortion, the adjacent channel leakage ratio (ACLR) reaches −45.5dBc at an average output power of 43.0 dBm, which can satisfy the requirements of the IMT-Advanced systems.

In this paper we present a 1.0-3.0 GHz GaN power amplifier with significant back-off power added efficiency (PAE) enhancement. The design of the PA, which has two digitally controlled RF inputs, was derived from a practical combining network without assuming any idealized conditions at the higher harmonics. By using linear multi-harmonic calculations, a GaN PA design was optimized for high efficiency with a 6.7 dB peak to average power ratio (PAPR) WCDMA signal over 108% fractional bandwidth. Measurements on the assembled circuit demonstrated 44 ± 0.9 dBm maximum output power, and a drain efficiency and PAE at 6 dB output power back-off (OPBO) larger than 48% and 45%, respectively.

This paper presents a Doherty power amplifier (DPA) controlled by the optimized bi-level supply modulator to improve an overall efficiency. By utilizing the supply modulation method determined by the probability density function (PDF) of an interest signal, an estimated average efficiency can be improved as much as 8.5 % compared with that of conventional DPA. For the verification the proposed DPA using commercial 120 W GaN devices has been devised. The experimental results show that the proposed DPA delivers a drain efficiency (DE) of 53.8 % and power added efficiency (PAE) of 50 %, with a gain of 11.8 dB at an average output power of 34.7 W for a 2.65 GHz 10 MHz 3G LTE signal with a 9 dB peak-to-average power ratio (PAPR). The measure result reveals that the DE of proposed DPA is 6 % higher than that of conventional one.

A switching power amplifier (PA) architecture that offers up to 13 dB of output power back-off without any drain efficiency degradation is presented. The proposed zero-voltage-switching (ZVS) contour-based PA employs a series class-E PA in conjunction with duty cycle modulation and a proposed tunable impedance transformation network. So-called ZVS conditions that ensure ideally 100% drain efficiency are satisfied not just at peak output power, but over the 13-dB back-off range. Theoretical analyses of losses in the PA and the impedance transformation network are also presented to prove that drain efficiency actually improves with back-off. Measurement results of a 100-MHz PA built using discrete components on an FR4 printed circuit board showing drain efficiency greater than or equal to the peak efficiency (40%) at all output power levels are also presented.