Simplified FPGA-based data acquisition system for PET

Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

Field Programmable Gate Arrays (FPGAs) are increasingly being used as a key component of digital systems because of their in-fieldreprogrammability, low non-recurring engineering costs (NRE), andrelatively short design cycle. Recently, there has been greatinterest in using FPGAs within spacecraft. FPGAs, like allsemiconductor devices, are susceptible to the effects of radiation.There is an active research community investigating the effects ofradiation on FPGAs and developing methods to mitigate against theseeffects. There has been significant progress over the last decade inthe understanding and developing FPGA technology that is resistant tothe effects of radiation. The success of FPGAs within spacecraftsuggests that FPGAs may be used in particle physics experiments whereradiation levels are considerable higher than the conventionalterrestrial earth environment. This paper will summarize the effectsof radiation on FPGAs, methods to mitigate against these effects,provide a case study of a successful FPGA system operating in space,and discuss the issues that will affect the use of FPGAs withinparticle physics experiments.

Field Programmable Gate Array Reliability Analysis Using the Dynamic Flowgraph Methodology

Field Programmable Gate Arrays (FPGAs) have gained popularity because their reconfigurability can speed up development and verification with relatively low cost. However the deep level of understanding required on hardware logic programming has discouraged many software engineers. An interface between host devices and FPGAs to enable designing and programming FPGAs using a software programming standard and encapsulating hardware details is much desired. In this paper we evaluate leveraging Open Computing Language (OpenCL) to rapidly design FPGAs, considering both hardware logic utilization efficiency and computing performance. On a heterogeneous computer system consisting of ARM processors and Altera FPGA, we execute an OpenCL host program on the ARM processors and an OpenCL kernel on the FPGA, to compute a parametrizable two-dimensional Mandelbrot fractal. We explore three design aspects of adjusting OpenCL work-group size, coalescing memory access, and replicating compute units to improve the FPGA computation performance. After optimizing the core algorithm, we efficiently reduced the logic utilization and Digital Signal Processing (DSP) blocks required for a single compute unit, and successfully increased the number of replicated compute units from four to six, thus delivering a 1.5X increase of parallel computation capacity of the FPGA, and improving the computing speed by 1.5X and memory bandwidth by 1.7X.

Field Programmable Gate Arrays (FPGAs), as any other electronic devices, are designed according to some life expectancy figures. For this reason, its lifetime is finite given due to appearance of faults caused by the natural physical degradation. In this paper, we present a low cost solution for autonomous detection of faults at the end of FPGAs life cycle. Our proposed methodology starts from a pre-analysis of memory elements belonging to modules under verification. Then, with a proper organization, it is created a list of all memory elements, controlled through a Built-In Self-Test (BIST) implementation via the FPGAs Internal Configuration Access Port (ICAP). By means of this list, a virtual scan chain is created, where the vectors (test and result) are written and read using the FPGA reconfiguration capabilities, which means there is no extra hardware to create the physical scan chain. The detection algorithm is implemented in the available system processing unit. The results show that with a minor increase in the program memory of the digital design, it is possible to perform an offline hardware testing of each sub-module in the existing FPGA, with no need of stopping the remaining of the system.

Currently, in few countries, there have been many projects related to the development of Field Programmable Gate Array (FPGA)-based Instrumentation and control (I&C) system designs for their nuclear power plant (NPP), whether for modernization or the new development of NPPs. Indonesia already develops a study related to High Temperature Gas Cooled Reactor as the generation IV for NPPs type for these few years with a specific type which is High Temperature Reactor–10 MW (HTR-10). Since the FPGA-based technology is new in the field, and both the international standards and guidance, from national and international has not defined provisions this issue, therefore verification and validation (V&V) activities for this HTR-10 are mandatory to be included in the design life cycle of I&C system development to get license approval from the national regulatory body. The FPGA-based system needs concentration both in hardware and software development, but commonly only software-related standards that usually included in the design and V&V in the previous computer-based I&C system. Therefore, in this study the V&V plan needs to be developed to state the methods to be required regarding the correctness of the applications of FPGA based I&C system. By arranging this V&V method, we will see whether they are easily applicable to actual systems, had the result to reach the requirement to have reliability, availability, maintainability and safety aspects, and has shortened and easier V&V step than computer-based I&C system. From the results of this study, it can be seen that the results of the method used for V&V between Programmable Logic Controller (PLC)-based and FPGA are almost the same because both have almost the same requirements, especially in software design. Some testing is not mandatory for FPGA-based because of the reduced system complexity. The use of FPGA can shorten the V&V process which can also reduce costs.

This paper presents a practical and low cost design-for-testability (DFT) scheme for the row-based field programmable gate array (FPGA) which is widely used for rapid prototyping, hardware verification/emulation of VLSI chips and manufacturing of complex digital systems. A new module is introduced for the DFT of the FPGA. The proposed DFT scheme permits the uncommitted FPGA to be tested using a set of constant cardinality (C-testability) for single and multiple stuck-at fault detection, while reducing the number of required primary test pins to only one. The number of tests for the FPGA is still 8+n/sub f/ (where n/sub f/ is the number of sequential modules in a row of the array), but only one primary pin and a small amount of testing circuitry are now required. This paper also modifies the single fault test set to accomplish multiple fault detection under two multiple fault models: the multiple fault single module (MFSM) and the single fault multiple module (SFMM) models. It is shown that by appropriately changing the don't care entries in the vectors of the test set for single fault detection, 100% and nearly 100% fault coverages can be achieved under the MFSM and SFMM models respectively.

Field programmable gate arrays (FPGAs) have drawn wide attention from nuclear power industry for digital instrument and control applications (DI&C), because it’s much easier and simpler than microprocessor-based applications, which makes it more reliable. FPGAs can also enhance safety margins of the plant with potential possibility for power upgrading at normal operation. For these reasons, more and more nuclear power corporations and research institutes are treating FPGA-based protection system as a technical alternative. As nuclear power industry requires high reliability and safety for DI&C Systems, the development method and process should be fully verified and validated. For this reason, to improve the application of FPGA in NPP I&C system, the specific test methods are critical for the developers and regulators. However, current international standards and research reports, like IEC 62566 and NUREG/CR-7006, which have demonstrated the life circle of the development of FPGA-based safety critical DI&C in NPPs, but the specific test requirements and methods which are significant to the developers are not provided. In this paper, the whole test process of a pressurized water reactor (PWR) protection sub-system (Primary Coolant Flow Low Protection, Over Temperature Delta T Protection, Over Power Delta T Protection) is described, including detail component and integration tests. The Universal Verification Methodology (UVM) based on System Verilog class libraries is applied to establish the verification test platform. All these tests are conducted in a simulation environment. The test process is driven by the test coverage which includes code coverages (i.e., Statement, Branch, Condition and Expression, Toggle, Finite State Machine) and function coverage. Specifically, Register Transaction Level (RTL) simulation is conducted for Component tests, while RTL simulation, Gate Level simulation, Timing simulation and Static timing analysis are conducted for the integration test. The issues (e.g., the floating point calculation, FPGA resource allocation and optimization) arose in the test process are also analyzed and discussed, which can be references for the developers in this area. The component and integration tests are part of the Verification and Validation (V&V) work, which should be done by the V&V team separated from the development team. The testing method could assure the test results reliable and authentic. It is practical and useful for the development and V&V of FPGA-based safety DI&C systems.

With the advancements in utilizing Artificial Intelligence (AI) in embedded safety-critical systems based on Field-Programmable Gate Arrays (FPGAs), assuring that these systems meet their safety requirements is of paramount importance for their revenue service. Based on this context, this paper has two main objectives. The first of them is to present the Safety ArtISt method, developed by the authors to guide the lifecycle of AI-based safety-critical systems, and emphasize its FPGA-oriented tasks and recommended practice towards safety assurance. The second one is to illustrate the application of Safety ArtISt with an FPGA-based braking control system for autonomous vehicles relying on explainable AI generated with High-Level Synthesis. The results indicate that Safety ArtISt played four main roles in the safety lifecycle of AI-based systems for FPGAs. Firstly, it provided guidance in identifying the safety-critical role of activities such as sensitivity analyses for numeric representation and FPGA dimensioning to achieve safety. Furthermore, it allowed building qualitative and quantitative safety arguments from analyses and physical experimentation with actual FPGAs. It also allowed the early detection of safety issues—thus reducing project costs—and, ultimately, it uncovered relevant challenges not discussed in detail when designing safety-critical, explainable AI for FPGAs.

FPGAs (Field-Programmable Gate Array) may offer higher performance than CPU architectures. Hardware Description Languages (HDL), such as VHDL and Verilog, which are traditionally used to program FPGAs, are known as hard to learn, to use, and to debug. Optionally, High Level Synthesis (HLS), such as OpenCL, allows developers to focus on the design of functions following a high-level software development flow, makes it easier to program FPGAs. This paper implements an image filter in the frequency domain on an FPGA board by using OpenCL, making the FPGA board an accelerator device to the host PC. The experiment results show that the filter implemented on the FPGA device can be optimized by pipelining the signal processing tasks onto the FPGA and reduce the I/O requirements between host PC and FPGA. The optimized FPGA implementation has higher performance than the image filter totally implemented on CPU.

Most underwater acoustic modems offer only low data rates. This is largely because they operate at low frequency, which limits the channel bandwidth available, and hence the symbol rate. The low frequency acoustic channel suffers from substantial multipath and doppler effects, which constrain the signal quality at the receiver. As a result only 1 or 2 bits per symbol are achieved, with the effective data rate further reduced by error control coding. High frequency acoustic signals are heavily attenuated in water, severely constraining the range of high frequency links. High frequency signals however offer substantially greater signal bandwidth, and probably improved channel quality which guides our design choice of a high frequency acoustic modem for underwater communication. Contemporary Field Programmable Gate Arrays (FPGAs) can provide good system functionality at low cost and with the flexibility to perform rapid testing and development of communication algorithms. They may also be competitive in production systems. In this paper we describe current progress in development of a high frequency, high data-rate modem which is implemented entirely in FPGA. This differs from most existing modems which are based on DSP processors. Being software defined, the modem is flexible because the parameters can be reconfigured with relative ease, minimising the cost of rework as the design evolves. This modem will not only demonstrate the feasibility of high frequency FPGA based modems, but will also be a valuable tool to provide a better understanding of the high frequency acoustic channel, and demonstrate the utility of absorption to enhance channel re-use rates in underwater acoustic networks. The modulator has been implemented in the FPGA, to produce laboratory and open water tests that conform to modelling. The demodulator has been implemented in Matlab, and recovers the carrier, code synchronisation and data from recordings of both laboratory and open water tests. Coding of the demodulator into the FPGA is currently in progress.

FPGA-based implementation of intelligent predictor for global solar irradiation, Part I: Theory and simulation

ICA (Independent Component Analysis) technique can be used to detect difference in sequence of images. However, the algorithm is usually highly computation intensive. In this paper, FPGA (Field Programmable Gate Array) implementation to speed up the computation of a non-iterative algebraic ICA is described. System level approach to the design of FPGA prototype is explained. Although FPGA does not offer an optimized hardware implementation when compared to ASIC (Application Specific Integrated Circuit), it allows short development time and enables verification of algorithms in hardware at a low cost.

In this paper, we developed a performance-enhanced, stand-alone dexterous robot hand with effective mechanical structure and lightweight control hardware. In the context, the paper shows the design methodology of HIT/DLR dexterous robot hand II controller using FPGA (field programmable gate array). Lower level controller is implemented in an FPGA and higher level controller is implemented in a DSP. Instead of a conventional architecture, a FPGA-based soft processor core is utilized. It includes a set of custom peripheral cores, such as data collection, brushless DC motors control and communication with palm's FPGA by point-to-point serial communication (PPSeCo). FPGAs make modular fingers more versatile, adding some new features to the design of hand like real-time control, hardware reuse, lower cost, fault-recovering, and software/hardware co-design. Finger control system use the NIOS soft CPU as hardware platform and uC/OS II real-time operating system as software platform to improve the efficiency of the system and short the responding time of a task. The experiment results clearly illustrate the high performance of the control system

This paper presents a hardware implementation of multilayer feedforward neural networks (NN) using reconfigurable field-programmable gate arrays (FPGAs). Despite improvements in FPGA densities, the numerous multipliers in an NN limit the size of the network that can be implemented using a single FPGA, thus making NN applications not viable commercially. The proposed implementation is aimed at reducing resource requirement, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The sequential processing of the layers in an NN has been exploited in this paper to implement large NNs using a method of layer multiplexing. Instead of realizing a complete network, only the single largest layer is implemented. The same layer behaves as different layers with the help of a control block. The control block ensures proper functioning by assigning the appropriate inputs, weights, biases, and excitation function of the layer that is currently being computed. Multilayer networks have been implemented using Xilinx FPGA "XCV400hq240". The concept used is shown to be very effective in reducing resource requirements at the cost of a moderate overhead on speed. This implementation is proposed to make NN applications viable in terms of cost and speed for online applications. An NN-based flux estimator is implemented in FPGA and the results obtained are presented.