Simulation and performance evaluation of parallel software on multiprocessor systems

User interface management graphics standards: Gallop, J RInformation Software Technol. Vol 29 No 4 (May 1987) pp 202–206

A commercial off-the-shelf (COTS) parallel processing system, consisted of multi-DSPs and a control computer, is used as a hardware platform for the online simulation of waveforms in the front end of sonar. The simulation system should be kept open and be run in real time, so the design issues for the simulation software in the multi-DSPs platform were addressed. The task parallel mode of the simulation system was designed. The program framework of DSP process was defined as active object based on object-oriented for the pipeline stage being smartly mapped onto DSP. Latency-tolerance technology was used for the design of data communications between DSP. Practices show that the constructed simulation system runs in real-time and can be modified easily and reconfigured that are usually difficult for the multi-task parallel DSP system.

We develop a new method to map (i.e. allocate and schedule) real-time applications into certain multiprocessor systems. Its objectives are: the minimization of the number of processors used; and the minimization of the deadline missing time. Given a parallel program with real time constraints and a multiprocessor system, our method finds schedules of the program in the system which satisfy all the real time constraints with minimum number of processors. The minimization is carried out through a Pareto-based genetic algorithm which independently considers the both goals, because they are non-commensurable criteria. Experimental results show that our scheduling algorithm achieved better performance than previous ones. The advantage of our method is that the algorithm produces not a single solution but a family of solutions known as the Pareto-optimal set, out of which designers can select optimal solutions appropriate for their environmental conditions.

The problem of optimal scheduling n tasks in a parallel processor system is studied. The tasks are malleable, i.e., a task may be executed by several processors simultaneously and the processing speed of a task is a nonlinear function of the number of processors allocated to it. The total number of processors is m and it is an upper bound on the number of processors that can be used by all the tasks simultaneously. It is assumed that the number of processors is sufficient to process all the tasks simultaneously, i.e. n≤m. The objective is to find a task schedule and a processor allocation such that the overall task completion time, i.e. the makespan, is minimized. The problem is motivated by real-life applications of parallel computer systems in scientific computing of highly parallelizable tasks. An O(n) algorithm is presented to solve this problem when all the processing speed functions are convex. If these functions are all concave and the number of tasks is a constant, the problem can be solved in polynomial time. A relaxed problem, in which the number of processors allocated to each task is not required to be integer, can be solved in O(nmax {m,nlog 2 m}) time. It is proved that the minimum makespan values for the original and relaxed problems coincide. For n=2 or n=3, an optimal solution for the relaxed problem can be converted into an optimal solution for the original problem in a constant time.

The number of processors is increasing, but the usefulness of parallel computation is not better leveraged due to the inflexibility of design and implementation for multiprocessor embedded system applications. A higher level abstraction (i.e., a parallel programming framework) can ease the programmers to define parallelism for tasks in an application but designers still face the complexity of mapping high-level requirements to the syntax and semantics of a parallel programming interface. Nevertheless, embedded system applications execute various periodic tasks that are carried out repeatedly within a certain time interval and these tasks may be able to run in parallel to utilize the system efficiently. Therefore, in this paper, we propose a parallel loop-based task construct approach to automate the design process of embedded system applications from AADL models for a parallel programming framework. To illustrate the applicability of our mechanism, we use a well-known parallel programming interface called OpenMP to demonstrate the automation process in mapping tasks over multiple processor cores. To ensure meeting high-level requirements of embedded system applications, we analyze the existing OpenMP scheduling mechanisms and propose a layer of adaptation. We show that our proposed adaptation layer facilitates a tighter execution time bound for time-sensitive tasks or a better throughput for tasks that require higher quality of service. Thus, the proposed design automation framework is applicable for a variety of applications with different quality of service (QoS) requirements preserved at the lower level.

For better utilization of computing resources, it is important to consider parallel programming environments in which the number of available processors varies at runtime. In this paper, we discuss runtime support for data parallel programming in such an adaptive environment. Executing data parallel-programs in an adaptive environment requires redistributing data when the number of processors changes, and also requires determining new loop bounds and communication patterns for the new set of processors. We have developed a runtime library to provide this support. We also present performance results for a multiblock Navier-Stokes solver run on a network of workstations using PVM for message passing. Our experiments show that if the number of processors is not varied frequently, the cost of data redistribution is not significant compared to the time required for the actual computations. >

Code scalability, crucial on any parallel system, determines how well parallel code avoids becoming a bottleneck as its host computer is made larger. The scalability of computer code can be estimated by statistically designed experiments that empirically approximate a multivariate Taylor expansion of the code's execution response function. Each suspected code bottleneck corresponds to a first‐order term in the expansion, the coefficient for that term indicating how sensitive execution is to changes in the suspect location. However, it is the expansion coefficients for second‐order interactions between code segments and the number of processors that are fundamental to discovering which program elements impede parallel speedup. A new, unified view of these second‐order coefficients yields an informal relative scalability test of high utility in code development. Discussion proceeds through actual examples, including a straightforward illustration of the test applied to SLALOM, a complex, multiphase benchmark. A quick graphical shortcut makes the scalability test readily accessible.

This paper proposes a parallel processing system -Harray- for scientific computations. Data flow computers are expected to obtain the high performance because they can extract parallelism fully from a program. However, they have many problems, such as the difficulty of controlling the sequence of execution. The -Harray- system is an array processor which adapts two levels of control mechanism; data flow execution in each processor and control flow between processors, in order to take full advantage of both mechanisms. A task which is assigned to a processor is called a “macro-block”. Three types of macro-blocking and three types of activation schemes for the macro-block which initiates its execution are introduced in order to attain the high performance. Moreover, a hardware synchronization mechanism is used to reduce synchronization overhead and to gain the liner speedup of the -Harray- system.In this paper, the system architecture of the -Harray- system and its performance evaluation by software simulation are presented.

Introducing new communication equipment or system to the Tracking and Data Relay Satellite System (TDRSS) ground segment is a complicated process that involves a lengthy development and test cycle. Complexity arises due to the presence of the variety of signaling formats, operation and user constraints, monitor and control parameters, and the requirement to ensure the new piece of ground equipment or system meets the functional and performance requirements for all different combinations of system configuration parameters and operational scenarios. The development cycle starts with extensive software simulations to establish the performance parameters of the new equipment or system followed by a prototyping stage. The prototype system undergoes a battery of tests in a laboratory environment to verify that it is capable of meeting the performance levels derived from the software simulations. Testing must be performed using simulated signals generated either using software or hardware. The current practice is to use a chain of test equipment, each piece in the chain dedicated to a single function. This requires manual setup between different test configurations and test reporting is also handled manually. This is costly both in terms of test hardware investment and the manpower involved. The options available to reduce the cost are to use either a software or hardware simulator that can combine multiple functions in a single unit. Software simulation involves generating signal files that can be played back repeatedly. Depending on the data rate being simulated, each test file can occupy several Terabytes (TBs); in addition, it requires a playback system which tends to be relatively expensive to acquire and maintain. On the other hand, with more advanced signal processing technology the hardware simulation can be achieved with low cost Field Programmable Gate Array (FPGA). A low cost hardware simulator that can support data rates up to 25 Mbps is selected for the simulation system. The simulator supports baseband digital data formats and different modulation and coding schemes used in the TDRSS. Channel impairments applicable for communicating with orbiting platforms and signal impairments generated by the TDRSS itself are also simulated by the system; these include stressing profiles of delay, Doppler, and multipath. Hardware distortions of customer platforms are simulated by a set of software defined distortion filters designed according to the user constraints specified in the Space Network user's guide. In order to reduce the time spent during the prototype testing phase, an automated test system is being developed. Simulator architecture and the test automation approach will be presented.

Some radar image processing algorithms such as shape-from-shading are particularly compute-intensive and time consuming. If, in addition, a data set to be processed is large, then it may make sense to perform the processing of images on multiple workstations or parallel processing systems. We have implemented shape-from-shading, stereo matching, resampling, gridding and visualization of terrain models in such a manner that they execute either on parallel machines or on clusters of workstations. We were motivated by the large image data set from NASA's Magellan mission to planet Venus, but received additional inspiration from the European Union's Center for Earth Observation program (CEO) and Austria's MISSION initiative for distributed processing of remote sensing images on remote workstations, using publicly accessible algorithms. We have developed a multi-processor approach that we denote as CDIP for Concurrent and Distributed Image Processing. The speedup for image processing tasks increases nearly linearly with the number of processors, be they on a parallel machine or arranged in a cluster of distributed workstations. Our approach adds benefits for users of complex image processing algorithms: the efforts for code porting and code maintenance are reduced and the necessity for specialized parallel processing hardware is eliminated.

In recent years, many commercial Massively Parallel Processor (MPP) systems have been available available to the computing community. These systems provide very high processing power (up to hundreds of GFLOPs), and can scale efficiently with the number of processors. However, many scientific and commercial applications that run on these multiprocessors may not experience significant benefit in terms of speedup and are bottlenecked by their I/O requirements. Although these multiprocessors may be configured with sufficient I/O hardware, the file system software often fails to provide the available I/O bandwidth to the application, and causes severe performance performance degradation for I/O intensive applications. A highly efficient parallel file system has been implemented on Intel's Teraflops (TFLOPS) machine and provides a sustained I/O bandwidth of 1 GB/sec. This file system provides almost 95% of the available raw hardware I/O bandwidth and the I/O bandwidth scales proportional to the available I/O nodes. Intel's TFLOPS machine is the first Accelerated Strategic Computing Initiative (ASCI) machine that DOE has acquired. This computer is 10 times more powerful than the fastest machine today, and will be used primarily to simulate nuclear testing and to ensure the safety and effectiveness of the nation's nuclear weapons stockpile. This machine contains over 9000 Intel's Pentium Pro processors, and will provide a peak CPU performance of 1.8 teraflops. This papers presents the I/O design and architecture of Intel's TFLOPS supercomputer, describes the Cougar OS I/O and its interface with the Intel's Parallel File System.

he analysis of any hardware or software from the point of view of the actual and possible performance is crucial in the computer world. Huge efforts are made to create newer, better and faster computers and programs while minor design flaws can result in very low performance not even worth the invested money. Many scientists focus their research on the performance analysis of different areas like parallel programs, PC clusters, shared memory architectures, supercomputers, cache performance and so on. Basically, two approaches can be found in this effort. One group of researchers try to create analitical models to calculate the performance and limits “in theory” while the other group implements monitoring tools to collect as much data about real executions as they can and then process this data and find bottlenecks in the performance. The first session of the workshop deals with performance analysis issues of different areas in computer science. The performance of PC clusters is analysed here as well as parallel applications with the need of the power of a teraflop supercomputer. Simulator for low-level interconnection networks is presented as well as mathematical models for parallel programs. Every researcher aims at making possible to the users to improve the performance of their system and their applications. The first paper is “Beowulf Performance in CFD Multigrid Applications” authored by F. Tirado, C. Garcia, R.S. Montereo, M. Prieto and I.M. Llorente. Authors evaluated the performance of a Beowulf-class system from the viewpoint of Computational Fluid Dynamics applications. They used two multigrid solvers to test their PC cluster with different configurations. The results show that, not surprisingly, the best configuration depends on the target application. The second paper presents “SICOSYS: An Integrated Framework for studying Interconnection Network Performance in Multiprocessor Systems” written by V. Puente, J.A. Gregorio and R. Beivide. SICOSYS is a generalpurpose simulator that makes possible the analysis of the interconnection networks of multiprocessor systems. This simulator has been integrated into the RSIM shared-memory-architecture and processor simulator as well as into the SimOS simulator that also includes the effects of an operating system into the simulation. The third paper presents new ideas about “Performance Analysis for Teraflop Computers: A Distributed Automatic Approach” authored by M. Gerndt, A. Schmidt, M. Schulz and R. Wismuller. A new performance analysis system has been designed for the monitoring and analysis of extremely computationally intensive applications on a teraflop computer. In such environment, classical analysis techniques fail because they are not scalable for thousands of processors. This paper presents the design of a new, automatic performance tool that is scalable on teraflop computers using a distributed approach for the analysis process. The fourth paper is the “Execution Time Prediction for Parallel Data Processing Tasks” written by S. Juhasz. This paper presents a mathematical model for execution time prediction in the domain of parallel programs with moderate computational power needs but working on large amount of data. A parallel sorting application is then analysed as an example.

We study the problem of scheduling periodic-time-critical tasks on a multiprocessor system. A periodic-time-critical task consists of a certain number of computations, each arising at a fixed interval of time, called the period of the task. The ratio of the computation time to the period is called the utilization factor of the task. Each computation has a prescribed deadline which must be guaranteed to be met, failing which there is likely to result an irrepairable loss. The scheduling problem is to specify the processor on which a computation is to be made and the order in which such computations will be made, such that every computation meets its deadline. The goal is to minimize the number of processors needed. The problem is NP-complete. As such, we devise a heuristic algorithm and analyze its performance. The algorithm assigns tasks based on the utilization factors of the tasks. We analyze the worst case performance of the algorithm by obtaining bounds on the ratio of the maximum number of processors needed by the algorithm to the minimum number of processors required. It is shown that this ratio is 2.

Parallel loops account for the greatest amount of parallelism in numerical programs. Executing nested loops in parallel with low run-time overhead is thus very important for achieving high performance in parallel processing systems. However, in parallel processing systems with caches or local memories in memory hierarchies, “thrashing problem” may arise.As thrashing problem severely ruins system performance, there has been an urgent need for a simple and effective algorithm to solve the problem.Based on thorough study of the relationship between the array element accesses and its enclosed loop indices in the nested loop,we present,in this paper,a set of compiler restructuring techniques,with which the reduced iteration space is staggered,regularized and compacted,the nested loop is restructured.As a result,we get a nested loop without thrashing problem and catering to different loop scheduling strategies.In addition to this, additional parallelism is exploited.KeywordsLocal MemoryNest LoopEquivalent ClassParallel Processing SystemMemory HierarchyThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Software simulation is one of the most common methods to study worm propagation. However, simulation process and software interface, which lack unified description, cause inefficiencies of worm propagation simulation. In order to achieve a unified description for worm propagation simulation process, we propose a Worm Propagation Simulation Description Language (WPSDL), which characterizes the software interfaces and parameters of each module in simulation process in a unified way. Meanwhile, we develop a simulation system of worm propagation oriented our presented language. In this system, we use related commands of the description language as interactive instructions, and then implement worm propagation simulation for different types of network worms. In addition, we conduct a series of experiments to analyse the impacts of worm propagation mechanism and network topology structure. The experiments show that increasing infection ability and scanning rate can improve the propagation scale significantly, and the propagation delay can influence the outbreak time and explosion intensity of worm propagation. The experiments not only provide support for the study of worm propagation mechanisms, but also verify the practicability of the description language and the simulation system.