Simulation-based work load and job release control for semiconductor manufacturing

The forecast of process cycle time is difficult in an IC manufacturing system, especially in an environment with multiple products and various processes. In this paper, a simple forecast mechanism is developed to provide the forecast of a product's cycle time and product's remaining process cycle time, and other useful processing information. The proposed algorithm is based on a dynamic average of historical process data stored in a database to generate runtime, wait-time and hold-time information, and the results are further classified in terms of tool group (or tool), technology and stage-ID hierarchically. The product's remaining process cycle time can be obtained by looking for the product's state from on-line data in the database first, and then utilizing the product's operation flow table and the average process time given above to calculate it. For calculating product's cycle time, it works in a similar way. Since the run-time, wait-time and hold-time of each lot can be shown from the proposed algorithm, it is easy to forecast the operation bottleneck of the lot. This method is proved to be useful by testing in Fab 3 of TSMC (Taiwan Semiconductor Manufacturing Company).

A full-scale semiconductor manufacturing plant model was developed from a SEMATECH dataset using the computer software package EXTEND. The model was generated to study the complex interactions and characteristics of a semiconductor fabrication process. Equipment downtimes, process flow routes, and machine processing times were used to validate the model. Pilot runs of the model were used to determine simulation run times and data collection rates for the initial inventory and product cycle time measurements. The product cycle time results from the model at 95% capacity were within 63 hours (or 7%) of the SEMATECH cycle time measurements. These results demonstrate the accuracy of the simulation model built from the SEMATECH dataset. The full-scale model was set up to run special scenarios showing the effects of eliminating maintenance and changing product types. The full-scale model was compared to a small-scale model based on the same dataset to demonstrate the inadequacy of the validated small-scale model. A full-scale model is also useful for analyzing scheduling routines, detecting bottlenecks, and understanding machine relations in the semiconductor industry.

It is indispensable to observe and control cycle time and throughput in a semiconductor manufacturing line to achieve competitive semiconductor manufacturing. It is especially important to control cycle time because any events in the line can cause delay in the cycle time and it becomes impossible to remedy the delay. We previously reported that lot arrival intervals could affect normalized cycle time (X-factor) and that this was an important factor to determine cycle time in a semiconductor manufacturing line (Inoue et al. (2005). This time, we created a new model that observes cycle time conditions and is useful for analyzing cycle time degradation on a manufacturing line. We call it a conveyer belt model and have found that it is valuable when visualizing and analyzing cycle time conditions. The proposed new model combined with queue time theory gives us an effective analysis of cycle time. As a result, this model is effective in the pursuit of cycle time design.

The garment industry is one of the fastest-paced production environments, where speed and accuracy are crucial for meeting global customer demand. Cycle time plays an important role in satisfying the speed factor as it represents the overall time needed to produce a single piece of a product. Maintaining an appropriate cycle time is key to achieving production line balance. This study aims to analyze the cycle time of men's jacket production on a sewing line in an Indonesian garment industry by comparing the actual cycle time with the standard cycle time based on the operation breakdown for each production process step. Four significant discrepancies in actual cycle time were identified, ranging from 16% to 95%, indicating that the actual cycle time was significantly longer than the standard cycle time. The root cause of the highest cycle time was analyzed using Fishbone and 5 Whys analysis to understand the problem from each factor and sub-factor. Six improvement action plans were proposed and implemented, resulting in a 57.81% reduction in actual cycle time, from 127.66 seconds to 53.85 seconds, making it 17.66% faster than the standard cycle time. Furthermore, the total output per hour increased by approximately 216.67%, from 12 pieces to 38 pieces. This result implies that the study successfully identified the root of the problem on the sewing line and managed to increase production output.

In manufacturing, many important decision-makings are based on demand forecasting of products. However, so many uncertainties lead to demand forecasting error. Especially, semiconductor manufacturing is characterized by its short product lifecycle, which means only limited historical data of a single product can be used to support error evaluation and correction of demand forecasting model, while traditional forecasting error evaluation and correction methods need large sample size to ensure the quality of results. To solve this problem, a new method titled “Nonparametric Inter-Quartile Range” (NIQR), which combines nonparametric density kernel estimation with cumulative probability distribution function, is proposed for error evaluation and model selection, and second quartile is used to correct model’s forecasting error. Numerical experiments in semiconductor manufacturing are used to show the feasibility and effectiveness of the proposed NIQR method for small sample size from short lifecycle product.

Setting defect charts control limits to balance cycle time and yield for a tandem production line

The radical change in the economical situation affected the semiconductor manufacturing business. Recently COT (customer oriented technology a.k.a. IC foundry) business is gaining popularity in many semiconductor manufacturing companies. In this field of semiconductor manufacturing business, predicting and controlling the fabrication cycle time, work in process status and in-line data with maintaining the high yields and quality of the products are the most important factors in the success of the whole business. Although semiconductor fabrication, excluding the design and assembly stages where these two stages are optional in COT business, is process oriented, just like the FMS in traditional assembly oriented manufacturing system, flexibility plays a major role. In this paper, the authors model and analyze the COT semiconductor fabrication from the customer order to the delivery stage using time Petri net models. Then a method to obtain turn around time, work in process status and capacity on-line by analyzing the behavior of the model is proposed by the authors.

A Self-Directed Work Team (SDWT) was developed to transfer a polyimide process module from the research laboratory to our wafer fab facility for applications in IC specialty devices. The SDWT implemented processes and tools based on the integration of five manufacturing strategies for continuous improvement. These were: Leadership Through Quality (LTQ), Total Productive Maintenance (TMP), Cycle Time Management (CTM), Activity-Based Costing (ABC), and Total Employee Involvement (TEI). Utilizing these management techniques simultaneously, the team achieved six sigma control of all critical parameters, increased Overall Equipment Effectiveness (OEE) from 20% to 90%, reduced cycle time by 95%, cut polyimide manufacturing cost by 70%, and improved its overall team member skill level by 33%.

Many contractors prefer on‐site fabrication of rebar while others find that off‐site fabrication is more advantageous. The economics of on‐site and off‐site fabrication of rebar need to be compared on the basis of several factors that include the project environment, wages, labour considerations, the initial investment for equipment, waste of rebar, the cost of inventory, cycle time, and supply chain management. This study presents an economic comparison of the on‐site and off‐site fabrication practices of rebar by means of a simulation model that makes use of the factors mentioned earlier. The model is populated with actual data obtained from a trade centre project in Istanbul, Turkey. The article indicates that the off‐site fabrication practice would have been more costly than the on‐site practice in the project in Istanbul, a finding that was to be expected in circumstances that prevail in most developing countries.

The impact of lot-sizing on net profits and cycle times in the n-job, m-machine job shop with both discrete and batch processing

Accurate and speedy forecasts of production cycle time are key components that support the operation of modern semiconductor wafer fabricators. Estimates of cycle time can be obtained via simulation, but such an approach, though common, requires significant computational investment and model maintenance. Queueing network models and approximations for their performance can provide a viable alternative. As modern semiconductor manufacturing systems exhibit largely reentrant product routing, but contain essential probabilistic routes (for metrology and rework), prior mean cycle time approximation methods are not well suited to the system structure. In this paper, we extend the decomposition without aggregation (DWOA) approach – which is tailored to systems with deterministic routing – to allow for the existence of probabilistic paths. Numerical and simulation studies are conducted with numerous practically inspired datasets to assess the quality of the resulting mean cycle time approximations. The results reveal that our approach outperforms the existing mean cycle time approximations on datasets inspired by the semiconductor industry MIMAC benchmark datasets. For example, in MIMAC dataset 1, our mean cycle time approximations exhibit an average of 10.33% error compared to 18.82% error for existing approaches.

Multiple response optimization in a fully automated FAB: an integrated tool and vehicle dispatching strategy∗

In this paper, we consider semiconductor manufacturing processes that can be characterized by a diverse product mix, heterogeneous parallel machines, sequence-dependent setup times, a mix of different process types, i.e. single-wafer vs. batch processes, and reentrant process flows. We use dispatching rules that require the estimation of waiting times of the jobs. Based on the lead time iteration concept of Vepsalainen and Morton (1988), we obtain good waiting time estimates by using exponential smoothing techniques. We describe a database-driven architecture that allows for an efficient implementation of the suggested approach. We present results of computational experiments for reference models of semiconductor wafer fabrication facilities. The results demonstrate that the suggested approach leads to high quality solutions.

This paper presents a scheduling heuristic to aid the operators in semiconductor fabrication facilities (commonly referred to as fabs) in choosing what type of lots to process next and whether to change machine setup in order to reduce cycle time. Specifically, this study focused on developing a scheduling heuristic for ion implanters at Cirent Semiconductor (currently Agere Systems) in Orlando, Florida, where implanters are considered to be a bottleneck workstation. The re-entrant flow of production passes several times through the implanters at different stages of the wafer production, requiring changes to the current settings of the workstations and thus incurring a significant setup time. The scheduling heuristic aims at balancing workload levels for implanters processing jobs at different stages of the wafer production lifecycle. This is accomplished by first processing those jobs that contribute most to the increase in inventory levels at the bottleneck workstation. The measures used to evaluate the performance of the proposed heuristic were mean cycle time, mean work in process (WIP), and standard deviation of cycle time. The performance of the proposed heuristic was compared with the scheduling rules currently in use and other commonly used dispatching rules using a validated simulation model. Simulation results showed that the introduced heuristic performs better than all other rules in terms of mean cycle time and WIP in all cases, and better in terms of standard deviation of cycle time for most cases tested. The heuristic can be used at any bottleneck workstation that processes products at different stages of their production cycle and that requires a significant setup time.

Semiconductor wafer manufacturing is among the most complex manufacturing processes, and hence a capital-intensive endeavor. The most common non cost-related performance measures for a semiconductor manufacturing facility are machine utilization, production yield, throughput, and last but not least cycle time. We define cycle time as the time a lot of wafers needs to travel through the semiconductor wafer manufacturing process. The overall cycle time of a lot of wafers is the sum of the total processing times of a wafer, waiting times for all resources (such as operators, machines, tools, transportation system) needed for each processing step to become available, times elapsed during measurement and quality inspections, and the time the lot has spent in transportation.