Simulation environment for design and verification of Network-on-Chip and multi-core systems

Abstract

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The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip interconnection structures. However, such networks present designers with a large array of design parameters and decisions, many of which are critical to the efficient operation of NoC systems. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment that has been developed and implemented using SystemC, a transaction-level modeling language. The simulation environment consists of on-chip components as well as traffic generators, which can generate various types of traffic patterns. A set of simulation results demonstrates the types of parameters that can affect performance of on-chip systems, including topology, network latency and achievable throughput. The results also verify the modeling capabilities of the proposed environment.